Low-cost and two-cycle hardware structures of PRINCE lightweight block cipher

In this paper, low-cost and two-cycle hardware structures of the PRINCE lightweight block cipher are presented. In the first structure, we proposed an area-constrained structure, and in the second structure, a high-speed implementation of the PRINCE cipher is presented. The substitution box (S-box) and the inverse of S-box (S-box⁻¹) blocks are the most complex blocks in the PRINCE cipher. These blocks are designed by an efficient structure with low critical path delay. In the low-cost structure, the S-boxes and S-boxes⁻¹ are shared between the round computations and the intermediate step of PRINCE cipher. Therefore, the proposed architecture is implemented based on the lowest number of computation resources. The two-cycle implementation of PRINCE cipher is designed by a processing element (PE), which is a general and reconfigurable element. This structure has a regular form with the minimum number of the control signal. Implementation results of the proposed structures in 180-nm CMOS technology and Virtex-4 and Virtex-6 FPGA families are achieved. The proposed structures, based on the results, have better critical path delay and throughput compared with other's related works.     

8VSB芯片的层次式设计方法

提出了深亚微米下系统级芯片层次式版图设计的方法，并用该方法设计了HDTV信道解码芯片8VSB的版图。实例设计结果表明，该方法在节约面积、加速时序收敛方面效果明显，大大缩短了芯片设计周期。     

我国IC产业发展状况分析

本文分析了集成电路及其相关技术的现状和发展趋势。分析了国内集成电路产业状况和面临的课题。     

0. 6 􀀁m CMOS 雷达天线专用控制芯片设计

雷达系统中天线控制电路完成上位机的初始化和扫描角度控制,要求具有高可靠性和低静态电流,用专用集成电路进行设计具有明显优势.采用Verilog HDL语言描述了系统的逻辑功能,超前进位结构的加/减法器提高了电路的工作速度.利用0.6 μm CMOS工艺完成了天线控制电路的物理实现,芯片面积为1.695 mm×1.631 mm.     

现代高速网络设备核心部件——网络处理器技术分析

对现代高速网络设备的核心部件－－网络处理器的体系结构、功能进行分析，提出网络处理器中软件的基本并行算法设计思想，并探讨网络处理器技术的未来发展趋势。     

一种铁氧体移相驱动器专用集成电路

介绍了ＳＡ０１８铁氧体移相驱动器专用集成电路的工作原理，电路设计和实验结果。该电路的内部电路设计有双路激励驱动器，放大器，积分器和双路高速比较器等功能单元。将铁氧体移相器的激励驱动器和相位控制器融于一体，大大减少了铁氧体移相器的外围设计。     

Viterbi译码器的硬件实现

介绍了一种Vkerbi译码器的硬件实现方法。设计的基于硬判决的Viterbi译码器具有约束长度长（9)、译码深度深（64)的特点。为了兼顾硬件资源与电路性能两个方面，在设计中使用了4个ACS单元，并根据Xilinx Virtex系列FPGA的结构特点．利用FPGA内部的BlockRAM保存汉明距离和幸存路径，提高了译码速度。     

一种3V CMOS音乐集成电路的设计原理

介绍了一种数字式全定制音乐集成电路设计原理。对伪音阶发生器、节拍发生器等子电路作了较详细的叙述。采用这种原理可设计出单芯片驱动压电陶瓷和发光二极管的音乐集成电路，该电路无须外接电阻、电容，可存储数首歌曲；另外，还可设计出一种数字音频程控频率合成器，时钟为ｆ０时，可控频率范围为ｆ０２～ｆ０２Ｎ。     

A New Algorithm for the Elimination of Common Subexpressions in Hardware Implementation of Digital Filters by Using Genetic Programming

A new algorithm based on Genetic Programming (GP) for the problem of optimization of Multiple constant Multiplication (MCM) by Common Subexpression Elimination(CSE) is developed. This method is used for hardware optimization for DSP systems. A solution based on Genetic Programming is shown in this paper. The performance of the technique is demonstrated in one- and multi-dimensional digital filters with constant coefficients.     

ASIC可靠性管理探讨

本文简要阐述了可靠性管理的概念，在我所技术质量管理的基础上，从产品立项、设计、设计评审、流片、封装、考核到鉴定使用全过程，对ASIC可靠性管理进行了分析和探讨，强调各部门必须保证工作质量，强化可靠性管理，通过管理把高可靠性注入到产品中去。