A parity-preserving multi-input signature analyzer and its application for concurrent checking and BIST

In this paper a joint implementation of a parity preserving multi-input signature analyzer (PMISA) and a parity checker is described. The PMISA simultaneously can be used for concurrent checking and for testing of digital circuits. In the case of concurrent checking errors are detected by their erroneous parity. If a circuit is tested errors are detected either by their erroneous parity or by the erroneous signature of the PMISA. A possible scan-mode of the PMISA allows its application in a scan path with parity-encoded inputs and outputs of the combinational modules which are driven by register sets. In normal operation mode all the registers of the PMISA can be utilized as functional registers of the combinational circuit.     

边界扫描超越基本PCB测试

为了更好地认识边界扫描技术,在介绍边界扫描测试的基本原理的基础上,从元件编程和调试、内建自测试结构、远端测试三个方面阐述了边界扫描技术应用的新进展,并指出了边界扫描测试新的发展方向。     

一种低功耗系统芯片的可测试性设计方案

低功耗技术,如多电源多电压和电源关断等的应用,给现代超大规模系统芯片可测试性设计带来诸多问题。为此,采用工业界认可的电子设计自动化工具和常用的测试方法,构建实现可测试性设计的高效平台。基于该平台,提出一种包括扫描链设计、嵌入式存储器内建自测试和边界扫描设计的可测性设计实现方案。实验结果表明,该方案能高效、方便和准确地完成低功耗系统芯片的可测性设计,并成功地在自动测试仪上完成各种测试,组合逻辑和时序逻辑的扫描链测试覆盏率为98.2%。