An integrated dimensionality reduction and surrogate optimization approach for plant-wide chemical process operation

With liquefied natural gas becoming increasingly prevalent as a flexible source of energy, the design and optimization of industrial refrigeration cycles becomes even more important. In this article, we propose an integrated surrogate modeling and optimization framework to model and optimize the complex CryoMan Cascade refrigeration cycle. Dimensionality reduction techniques are used to reduce the large number of process decision variables which are subsequently supplied to an array of Gaussian processes, modeling both the process objective as well as feasibility constraints. Through iterative resampling of the rigorous model, this data-driven surrogate is continually refined and subsequently optimized. This approach was not only able to improve on the results of directly optimizing the process flow sheet but also located the set of optimal operating conditions in only 2 h as opposed to the original 3 weeks, facilitating its use in the operational optimization and enhanced process design of large-scale industrial chemical systems.     

2.3–21 GHz broadband and high linearity distributed low noise amplifier

This paper focuses on the design of a 2.3–21 GHz Distributed Low Noise Amplifier (LNA) with low noise figure (NF), high gain (S₂₁), and high linearity (IIP3) for broadband applications. This distributed amplifier (DA) includes S/C/X/Ku/K-band, which makes it very suitable for heterodyne receivers. The proposed DA uses a 0.18 μm GaAs pHEMT process (OMMIC ED02AH) in cascade architecture with lines adaptation and equalization of phase velocity techniques, to absorb their parasitic capacitances into the gate and drain transmission lines in order to achieve wide bandwidth and to enhance gain and linearity. The proposed broadband DA achieved an excellent gain in the flatness of 13.5 ± 0.2 dB, a low noise figure of 3.44 ± 1.12 dB, and a small group delay variation of ±19.721 ps over the range of 2.3–21 GHz. The input and output reflection coefficients S₁₁ and S₂₂ are less than −10 dB. The input compression point (P_1dB) and input third-order intercept point (IIP3) are −1.5 dBm and 11.5 dBm, respectively at 13 GHz. The dissipated power is 282 mW and the core layout size is 2.2 × 0.8 mm².     

Recent activities in the field of Nuclear Operational Management and Nuclear Safety Engineering

Recent activities in the field of Nuclear Operational Management and Nuclear Safety Engineering, the studies related to risk analysis methodology, design, and operational management, physical phenomena, and emergency preparedness and nuclear security, have been progressed. Especially, ‘risk analysis methodology’ and ‘design and operational management’ are the main categories of the field, in which more than half of published articles on Journal of Nuclear Science and Technology are related to these categories.     

提高催化裂化装置(FCCU)柴汽比措施

为了满足市场的需要,中石化天津分公司炼油厂根据FCCU自身特点采取了一系列提高柴汽比的措施,包括:调节反应系统和分馏的操作条件及采用MGD技术,以提高柴油产率。实施后,FCCU的柴汽比从0.5提高到0.9,创造了良好的经济效益。     

光纤参量放大器技术及其最新进展

介绍和论述了一种非常有实用前景的基于光纤非线性效应的光参量放大器(OPA)及其最新技术进展．最新发展揭示了它的很多技术特性优于传统的掺铒光纤放大器(EDFA)、半导体光放大器(SOA)和近年来很热门的光纤拉曼放大器(FRA)，如对信号的调制形式、比特率的完全透明性、相位共轭、超宽的增益带宽、很低的噪声指数和具备优异的全光波长转换功能．     

CMOS光接收机主放大器设计

利用CMOS工艺设计一种用于SDH STM 4速率级(622 Mb/s)光纤用户网的光接收机放大电路。此电路由输入/输出缓冲、主放大单元、偏置补偿电路4部分组成。通过直接耦合技术提高增益,降低功耗;利用有源电感负载提高系统带宽。采用商用SmartSpice电路仿真软件和CSMC HJ 0.6μm工艺参数对该电路进行仿真。结果表明,该电路在5 V工作电压下中频增益为81 dB,3 dB带宽为470 MHz。     

采用RF2607的WLAN自动增益控制设计

介绍了宽动态变化范围的新型可变增益放大器RF2607的特性、功能,给出了利用RF2607设计无线局域网(WLAN)通信中自动增益控制部分的实用电路.     

5Gb/s 0.25μm CMOS限幅放大器

采用TSMC 0.25μm CMOS技术设计实现了高速低功耗光纤通信用限幅放大器.该放大器采用有源电感负载技术和放大器直接耦合技术以提高增益,拓展带宽,降低功耗并保持了良好的噪声性能.电路采用3.3V单电源供电,电路增益可达50dB,输入动态范围小于5mVpp,最高工作速率可达7Gb/s,均方根抖动小于0.03UI.此外核心电路功耗小于40mW,芯片面积仅为0.70mm×0.70mm.可满足2.5,3.125和5Gb/s三个速率级的光纤通信系统的要求.     

光传送网中的关键光器件

光器件是光传送网的基础单元之一，本主要综述光传送网中的关键光器件：光源与光探测器、光波分复用/解复用器、光放大器、色度色散与偏振模补偿器及光开关等。比较了各种光器件的主要技术方案，特别针对的是已实用化的技术方案。最后讨论了光器件的尺寸小型化、微型化以及多功能集成等发展趋势，介绍了光器件的集成方式如：传统分立光器件的集成，平面光波导集成，以及混合集成等。     

宽工作电压范围单电源CMOS误差放大器

采用0.8μm标准数字CMOS工艺(VTN0=0.836V,VTP0=0.930V),设计并流片验证了具有宽工作电压范围(3～6V),可作SOC系统动态电源管理芯片内部误差放大器应用的单电源CMOS运算放大器。该误差放大器芯核同时具有适合低电压工作,并对工艺参数变化不敏感的优点。对于相同的负载情况,在3V的工作电压下,开环电压增益AD=83.1dB,单位增益带宽GB=2.4MHz,相位裕量Φ=85.2°,电源抑制比PSRR=154.0dB,转换速率Sr=2.2V/μs;在6V工作电压下,AD=85.1dB,GB=2.4MHz,Φ=85.4°,PSRR=145.3dB,Sr=3.4V/μs。