Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

As we approach 100 nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-on-chips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.     

CADRE: An Asynchronous Embedded DSP for Mobile Phone Applications

Asynchronous design techniques have a number of compelling features that make them suited for complex system on chip designs. However, it is necessary to develop practical and efficient design techniques to overcome the present shortage of commercial design tools. This paper describes the development of CADRE (Configurable Asynchronous DSP for Reduced Energy), a 750K transistor, high performance, low-power digital signal processor IP block intended for digital mobile phone chipsets. A short time period was available for the project, and so a methodology was developed that allowed high-level simulation of the design at the earliest possible stage within the conventional schematic entry environment and simulation tools used for later circuit-level performance and power consumption assessment. Initial modeling was based on C behavioral models of the various data and control components, with the many asynchronous control circuits required automatically generated from their specifications. This has enabled design options to be explored and unusual features of the design, such as the Register Bank which is designed to exploit data access patterns, are presented along with the power and performance results of the processor as a whole.     

Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test

A system-on-chip (SOC) usually consists of many memory cores with different sizes and functionality, and they typically represent a significant portion of the SOC and therefore dominate its yield. Diagnostics for yield enhancement of the memory cores thus is a very important issue. In this paper we present two data compression techniques that can be used to speed up the transmission of diagnostic data from the embedded RAM built-in self-test (BIST) circuit that has diagnostic support to the external tester. The proposed syndrome-accumulation approach compresses the faulty-cell address and March syndrome to about 28% of the original size on average under the March-17N diagnostic test algorithm. The key component of the compressor is a novel syndrome-accumulation circuit, which can be realized by a content-addressable memory. Experimental results show that the area overhead is about 0.9% for a 1Mb SRAM with 164 faults. A tree-based compression technique for word-oriented memories is also presented. By using a simplified Huffman coding scheme and partitioning each 256-bit Hamming syndrome into fixed-size symbols, the average compression ratio (size of original data to that of compressed data) is about 10, assuming 16-bit symbols. Also, the additional hardware to implement the tree-based compressor is very small. The proposed compression techniques effectively reduce the memory diagnosis time as well as the tester storage requirement.     

基于SoC的嵌入式DRAM存储器内建自测试设计

内建自测试(Built-in Self Test,BIST)是测试片上系统(System on- Chip,SoC)中嵌入式存储器的重要技术;但是,利用BIST技术采用多种算法对嵌入式存储器进行测试仍面临诸多挑战;对此,提出了一种基于SoC的可以带有多种测试算法的嵌入式DRAM存储器BIST设计,所设计的测试电路可以复用状态机的状态,利用循环移位寄存器(Cyclic Shift Register,CSR)产生操作命令,利用地址产生电路产生所需地址;通过对3种BIST电路支持的算法,全速测试,面积开销3个方面的比较,表明提出的嵌入式DRAM存储器BIST设计在测试时间,测试故障覆盖率和测试面积开销等各方面都取得了较好的性能.     

SoC自动化验证方法的研究与实现

为解决SoC（System-on-Chip）验证覆盖率和工作量问题,基于可重用思想、采用事务验证模型、随机激励生成的方法,建立了一个层次化的具有自主知识产权的自动化功能验证系统（LSAVS：LiShan Automatic Verification System）。采用该验证系统后,SoC验证工程师开发测试向量的工作量由使用传统验证方法的60%降低到10%,同时保证了功能验证100%的覆盖率,达到快速高覆盖率的验证目的。     

支持过程级动态软硬件划分的RSoC设计与实现

目前,可重构计算平台所支持的动态软硬件划分粒度多处于线程级或指令级,但线程级划分开销太大,而指令级划分又过于复杂,因此很难被用于实际应用之中。本文设计并实现了一种支持过程级动态软硬件划分的可重构片上系统(RSoC),提出了一种过程级硬件透明编程模型,给出了过程级的硬件封装方案;在分析软硬件过程根本区别的基础上,针对硬件过程开发了专门的管理模块,并利用部分动态重构等技术,实现了硬件过程的动态配置。实验表明该系统能够较好的支持过程级的动态软硬件划分,实现了节省资源、简化设计,提高性能等目的。     

SoC测试访问机制和测试壳的蚁群联合优化

针对系统级芯片(SoC)测试壳优化和测试访问机制的测试总线划分问题,提出了基于蚁群算法的SoC Wrapper/TAM联合优化方法.构造蚁群算法时首先进行IP核的测试壳优化,用于缩短最长扫描链长度,减少单个IP核的测试时间;在此基础上进行TAM结构的蚁群优化,通过算法迭代逼近测试总线的最优划分,从而缩短SoC测试时间.对ITC2002基准SoC电路进行实验的结果表明,该方法能有效地解决SoC测试优化问题.     

过程级动态划分的RSoC软硬件双通信模式

软硬件通信模式的选择对软硬件通信效率产生很大影响.根据硬件函数的特点,提出一种根据软硬件通信量自适应地选择通信模式的软硬件双通信模式,并构建了一种通信模式自适应决策算法,软硬件通信模式的选择对用户透明.实验表明,根据运行时系统状态自适应地选择通信模式,软硬件通信效率得到优化,面积开销也适当减少.     

FPGA的动力电池检测系统研究

为提高动力电池使用效率,提出了一种基于FPGA的动力电池检测系统的设计方案.采用AD转换芯片实现对电池电压、电流的采集,数字温度传感器对温度进行采集,再通过软件实现对数据的处理和实时显示.系统运行稳定,数据处理能力强,集成度高,易于扩展.     

SCV及其在SoC验证中的应用

片上系统(System on Chip,SoC)是集成电路设计发展的趋势,验证在整个SoC设计中工作量巨大且至关重要.应用验证领域的最新成果SCV(SystemCVerification),提出了通过设计用户定义的事务接口(Transactor),对RTL(RegisterTransferLevel)级设计进行事务级验证的策略,并对一个具体的FIFO事例进行了验证.