一种用于FPGA的快速锁定全数字延时锁定环的设计实现

本文提出了一种用于FPGA中DDR SDRAM控制器的接口快速锁定的全数字延时锁定环。该电路对数据选择脉冲(DQS)实现90度的相位偏移。为了实现延时锁定环的快速锁定,同时解决了错误锁定的问题,本文提出了一种新颖的数字时间转换器的结构。在延时环路中设计了占空比纠正电路,实现50％的占空比输出。该延时锁定环电路采用0.13μm标准CMOS工艺设计制作。测试结果表明,工作频率范围为75MHz～350MHz,数字控制延时链(DCDL)的调节精度为15ps,并且电路的闭环特性能跟踪电压、温度等环境的变化。     

A fast-locking all-digital delay-locked loop for phase/delay generation in an FPGA

A fast-locking all-digital delay-locked loop(ADDLL) is proposed for the DDR SDRAM controller interface in a field programmable gate array(FPGA).The ADDLL performs a 90°phase-shift so that the data strobe(DQS) can enlarge the data valid window in order to minimize skew.In order to further reduce the locking time and to prevent the harmonic locking problem,a time-to-digital converter(TDC) is proposed.A duty cycle corrector(DCC) is also designed in the ADDLL to adjust the output duty cycle to 50%.The ADDLL,implemented in a commercial 0.13μm CMOS process,occupies a total of 0.017 mm~2 of active area.Measurement results show that the ADDLL has an operating frequency range of 75 to 350 MHz and a total delay resolution of 15 ps.The time interval error(TIE) of the proposed circuit is 60.7 ps.