Pipelined robust M-estimate adaptive second-order Volterra filter against impulsive noise

The main limits on adaptive Volterra filters are their computational complexity in practical implementation and significant performance degradation under the impulsive noise environment. In this paper, a low-complexity pipelined robust M-estimate second-order Volterra (PRMSOV) filter is proposed to reduce the computational burdens of the Volterra filter and enhance the robustness against impulsive noise. The PRMSOV filter consists of a number of extended second-order Volterra (SOV) modules without feedback input cascaded in a chained form. To apply to the modular architecture, the modified normalized least mean M-estimate (NLMM) algorithms are derived to suppress the effect of impulsive noise on the nonlinear and linear combiner subsections, respectively. Since the SOV-NLMM modules in the PRMSOV can operate simultaneously in a pipelined parallelism fashion, they can give a significant improvement of computational efficiency and robustness against impulsive noise. The stability and convergence on nonlinear and linear combiner subsections are also analyzed with the contaminated Gaussian (CG) noise model. Simulations on nonlinear system identification and speech prediction show the proposed PRMSOV filter has better performance than the conventional SOV filter and joint process pipelined SOV (JPPSOV) filter under impulsive noise environment. The initial convergence, steady-state error, robustness and computational complexity are also better than the SOV and JPPSOV filters.     

A nonlinearity error calibration technique for pipelined ADCs

This paper presents a digital background calibration technique that measures and cancels offset, linear and nonlinear errors in each stage of a pipelined analog to digital converter (ADC) using a single algorithm. A simple two-step subranging ADC architecture is used as an extra ADC in order to extract the data points of the stage-under-calibration and perform correction process without imposing any changes on the main ADC architecture which is the main trend of the current work. Contrary to the conventional calibration methods that use high resolution reference ADCs, averaging and chopping concepts are used in this work to allow the resolution of the extra ADC to be lower than that of the main ADC.     

Designing soft-edge flip-flop-based linear pipelines operating in multiple supply voltage regimes

Soft-edge flip-flop (SEFF) based pipelines can improve the performance and energy efficiency of circuits operating in the super-threshold (supply voltage) regime by enabling the opportunistic time borrowing. The application of this technique to the near-threshold regime of operation, however, faces a significant challenge due to large circuit parameter variations that result from manufacturing process imperfections. In particular, delay lines in SEFFs have to be over-designed to provide larger transparency windows to overcome the variation in path delays, which causes them to consume more power. To address this issue, this paper presents a novel way of designing delay lines in SEFFs to have a large enough transparency window size and low power consumption. Two types of linear pipeline design problems using the SEFFs are formulated and solved: (1) designing energy-delay optimal pipelines for the general usage that requires SEFFs to operate in both the near-threshold and super-threshold regimes, and (2) designing minimum energy consumed pipelines for particular use case with a minimum operating frequency constraint. Design methods are presented to derive requisite pipeline design parameters (i.e., depth and sizing of delay lines in SEFFs) and operating conditions (i.e., supply voltage and operating frequency of the design) in presence of process-induced variations. HSPICE simulation results using ISCAS benchmarks demonstrate the efficacy of the presented design methods.     

Pipelined Scheduling of Functional HW/SW Modules for Platform‐Based SoC Design

We developed a pipelined scheduling technique of functional hardware and software modules for platform‐based system‐on‐a‐chip (SoC) designs. It is based on a modified list scheduling algorithm. We used the pipelined scheduling technique for a performance analysis of an MPEG4 video encoder application. Then, we applied it for architecture exploration to achieve a better performance. In our experiments, the modified SoC platform with 6 pipelines for the 32‐bit dual layer architecture shows a 118% improvement in performance compared to the given basic SoC platform with 4 pipelines for the 16‐bit single‐layer architecture.     

Systematic design and modelling of high-resolution, high-speed pipeline ADCs

This paper describes a suitable mathematical model for the design of high-speed, high-resolution pipeline ADCs. The effect of capacitor mismatch and finite amplifier bandwidth and gain on the converter INL and DNL are accurately modelled. On the basis of this model a design optimisation method is provided.     

一种流水线型高速过采样∑-△调制器

提出了一种采用流水线采样输入的开关电容型∑－△调制器的实现方法，该方法充分利用了时钟的每一时刻。用此方法设计的∑－△调制器来样速率可提高３０％。实验表明，这种方法是完全可取的。     

一种流水型40 MSPS高速采样保持器

通过理论分析和实验仿真,提出了一种流水型高速采样保持器电路(S/H)。采用4个采样率为10 MSPS的S/H,构成一个流水型电路结构的S/H,采样率达到40 MSPS。文章提出的电路结构,在一定程度上解决了采样速率与精度的矛盾关系,可以在组合S/H精度等同于单个S/H精度的前提下,将组合S/H采样速率提高到单个S/H的数倍。     

一种新型的视觉计算机

视觉信息处理可以看作是从三维环境的图象中抽取、描述和解释信息的过程.根据该过程所涉及的方法和技术的复杂性,可将它们分成三个处理层次:低层视觉,中层视觉和高层视觉.作者根据各个层次视觉处理的要求和特点,提出分别采用基于DSP的低层视觉处理模块,中层视觉处理模块——PIPE以及高层视觉处理模块——并行图归约机(PGR).它们共用一个工作平台IBMPC,组成混合型视觉计算机.这可能是解决视觉信息处理复杂、数据量大以及实时要求高等问题的有效方法.     

Delay composition in preemptive and non-preemptive real-time pipelines

Uniprocessor schedulability theory made great strides, in part, due to the simplicity of composing the delay of a job from the execution times of higher-priority jobs that preempt it. In this paper, we bound the end-to-end delay of a job in a multistage pipeline as a function of job execution times on different stages under preemptive as well as non-preemptive scheduling. We show that the end-to-end delay is bounded by that of a single virtual “bottleneck” stage plus a small additive component. This contribution effectively transforms the pipeline into a single stage system. The wealth of schedulability analysis techniques derived for uniprocessors can then be applied to decide the schedulability of the pipeline. The transformation does not require imposing artificial per-stage deadlines, but rather models the pipeline as a whole and uses the end-to-end deadlines directly in the single-stage analysis. It also does not make assumptions on job arrival patterns or periodicity and thus can be applied to periodic and aperiodic tasks alike. We show through simulations that this approach outperforms previous pipeline schedulability tests except for very short pipelines or when deadlines are sufficiently large. The reason lies in the way we account for execution overlap among stages. We discuss how previous approaches account for overlap and point out interesting differences that lead to different performance advantages in different cases. Further, we also show that in certain cases non-preemptive scheduling can result in higher system utilization than preemptive scheduling in pipelined systems. We hope that the pipeline delay composition rule, derived in this paper, may be a step towards a general schedulability analysis foundation for large distributed systems.

一种应用于流水线A/D转换器的数字校准算法

通过输入比较器阈值电压到流水线电路计算跳变点高度，重新计算权重，进行数字校准。这种校准方法与数字冗余结合，属于纯数字电路实现，在可实现性与可靠性上具有很大的优势。仿真结果表明，这种方法能保证高精度。