Low voltage operating organic light emitting transistors with efficient charge blocking layer

Charge injection/blocking layers play important roles in the performances of organic electronic devices. Their incorporation into organic light emitting transistors has been limitted, due to generally high operating voltages (above 60 V) of these devices. In this work, two hole blocking molecules are integrated into tris-(8-hydroxyquinoline) aluminum (Alq₃) based light emitting transistors under operating voltage as low as 5 V. The effects of hole blocking and electron injection are decoupled through the differences in the energy levels. Significantly improved optical performance is achieved with the molecule of suitable energy level for electron injection. Surprisingly, a decreased performance is observed in the case of another hole blocking molecule evidencing that charge injection overweighs charge blocking in this device architecture.     

C8 BTBT薄膜结晶形貌及OTFT器件性能研究

以p型共轭有机小分子2,7二辛基[1]苯并噻吩并[3,2‐b]苯并噻吩(C8‐BTBT)作为底栅顶接触有机薄膜晶体管(OTFT)的有源层,采用浸渍提拉法、喷墨打印法和真空蒸镀法三种制备工艺,探究半导体薄膜载流子迁移率与结晶形貌的关系,发现不同工艺下有机小分子呈现出不同的生长行为和结晶情况,在很大程度上决定了OTFT器件性能的优劣;此外,通过XRD分析研究了退火处理对C8‐BTBT结晶的影响。结果表明,真空蒸镀制备的薄膜具有更高的结晶度、衬底覆盖率高,并且呈现出SK(Stranski‐Krastanov)模式的结晶生长特征,相应器件中陷阱密度最低,迁移率高达5.44 cm^2·V^-1·s^-1,开关比超过106;且退火处理会严重破坏C8‐BTBT薄膜的结晶。因此,控制半导体层的生长行为,提升半导体层的覆盖率和结晶度是制备高性能共轭小分子OTFT器件的有效途径。     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

Sol-gel processed high-k aluminum oxide dielectric films for fully solution-processed low-voltage thin-film transistors

High-k oxide dielectric films have attracted intense interest for thin-film transistors (TFTs). However, high-quality oxide dielectrics were traditionally prepared by vacuum routes. Here, amorphous high-k alumina (Al₂O₃) thin films were prepared by the simple sol-gel spin-coating and post-annealing process. The microstructure and dielectric properties of Al₂O₃ dielectric films were systematically investigated. All the Al₂O₃ thin films annealed at 300–600?°C are in amorphous state with ultrasmooth surface (RMS ~ 0.2?nm) and high transparency (above 95%) in the visible range. The leakage current of Al₂O₃ films gradually decreases with the increase of annealing temperature. Al₂O₃ thin films annealed at 600?°C showed the low leakage current density down to 3.9?×?10^?7 A/cm² at 3?MV/cm. With the increase of annealing temperature, the capacitance first decreases then increases to 101.1?nF/cm² (at 600?°C). The obtained k values of Al₂O₃ films are up to 8.2. The achieved dielectric properties of Al₂O₃ thin films are highly comparable with that by vapor and solution methods. Moreover, the fully solution-processed InZnO TFTs with Al₂O₃ dielectric layer exhibit high mobility of 7.23?cm² V^?1 s^?1 at the low operating voltage of 3?V, which is much superior to that on SiO₂ dielectrics with mobility of 1.22?cm²/V^?1 s^?1 at the operating voltage of 40?V. These results demonstrate that solution-processed Al₂O₃ thin films are promising for low-power and high-performance oxide devices.     

Using d-limonene as the non-aromatic and non-chlorinated solvent for the fabrications of high performance polymer light-emitting diodes and field-effect transistors

Aiming to environment protection, green solvents are crucial for commercialization of solution-processed optoelectronic devices. In this work, d-limonene, a natural product, was introduced as the non-aromatic and non-chlorinated solvent for processing of polymer light-emitting diodes (PLEDs) and organic field effect transistors (OFETs). It was found that d-limonene could be a good solvent for a blue-emitting polyfluorene-based random copolymer for PLEDs and an alternating copolymer FBT-Th₄(1,4) with high hole mobility (μ_h) for OFETs. In comparisons to routine solvent-casted films of the two conjugated polymers, the resulting d-limonene-deposited films could show comparable film qualities, based on UV–vis absorption spectra and observations by atomic force microscopy (AFM). With d-limonene as the processing solvent, efficient blue PLEDs with CIE coordinates of (0.16, 0.16), maximum external quantum efficiency of 3.57%, and luminous efficiency of 3.66 cd/A, and OFETs with outstanding μ_h of 1.06 cm² (V s)⁻¹ were demonstrated. Our results suggest that d-limonene would be a promising non-aromatic and non-chlorinated solvent for solution processing of conjugated polymers and molecules for optoelectronic device applications.     

In-plane light emission of organic light-emitting transistors with bilayer structure using ambipolar semiconducting polymers

The concept of using an ambipolar bilayer semiconducting heterostructure in organic light-emitting transistors (OLETs) is introduced to provide a new approach to achieve surface emission. The properties of top-gate-type bilayer OLETs with ambipolar materials based on two types of fluorene-type polymers used as an emissive layer and an electron blocking layer are investigated. Line-shaped yellow–green emission occurs near a hole-injection electrode. When hole transport is dominant in the upper layer which acts as an electron blocking layer, and electrons are injected into the lower layer, an in-plane light-emitting pattern is observed. The measured in-plane emission zone confirms that both hole and electron transport are determined to occur mainly along the different organic layers between the source and drain electrodes, and an in-plane recombination zone of electrons and holes exists near the bilayer organic interface. This work is anticipated to be useful for the development of in-plane light-emitting transistors.     

High-performance 2,9-DPh-DNTT organic thin-film transistor by weak epitaxy growth method

2,9-DPh-DNTT, an isomeric of diphenyl-dinaphtho[2,3-b:2′,3′-f]-thieno[3,2-b] thiophene (DPh-DNTTs), is an emerging candidate of high mobility organic semiconductor material. In this work, a high performance 2,9-DPh-DNTT organic thin-film transistor (OTFT) is fabricated by the method of weak epitaxy growth. The quality of 2,9-DPh-DNTT thin film was significantly improved when its epitaxial layer grows on an inducing layer of para-sexiphenyl (p-6P). Continuous large-area, highly ordered and terraced 2,9-DPh-DNTT polycrystalline thin films are obtained. The hole mobility of as-fabricated 2,9-DPh-DNTT thin-film transistor reaches up to 6.4 cm² V⁻¹s⁻¹. This simple process of preparing high mobility 2,9-DPh-DNTT thin-film transistor supplies a facile route of large-area OTFT fabrication.     

Maskless metal patterning by meniscus-confined electrochemical etching and its application in organic field-effect transistors

Conductive micropatterns is an essential part for operation of electronic devices in both industrial and academic fields. Conventional mask-based photolithography and vacuum deposition are inadequate to meet the demands of convenience and simplicity due to their complicated operation, costly instrumentations and relatively low resolution (for vacuum deposition). Development of simple and efficient mask-less fabrication techniques of conductive micropatterns is highly expected. Here we report a facile meniscus-confined electrochemical etching (MCEE) approach to fabricate metal micropatterns with resolution down to at least 1.0 μm. Both the applied bias and the moving velocity directly influence the patterning resolution. MCEE process is developed to fabricate source and drain electrodes in organic transistors on both rigid and flexible substrates. Being a maskless direct writing method, the width and morphology of the etched channel can be easily modulated by the bias and the velocity. The organic transistor with top-contact configuration presents better electrical performance with device on/off ratio of 1.1 × 10⁵ and maximum carrier mobility of 1.07 cm²V⁻¹s⁻¹, which implies that MCEE operation doesn't result in the degradation of the already deposited semiconducting film. This mask-less MCEE approach provides a potential complementary to conventional mask-based techniques for the fabrication of microscale metal patterns.     

THE effect of Srandom DOPANT fluctuation on threshold voltage and drain current variation in junctionless nanotransistors

We investigate the effect of dopant random fluctuation on threshold voltage and drain current variation in a two-gate nanoscale transistor. We used a quantum-corrected technology computer aided design simulation to run the simulation (10000 randomizations). With this simulation, we could study the effects of varying the dimensions (length and width), and thicknesses of oxide and dopant factors of a transistor on the threshold voltage and drain current in subthreshold region (off) and overthreshold (on). It was found that in the subthreshold region the variability of the drain current and threshold voltage is relatively fixed while in the overthreshold region the variability of the threshold voltage and drain current decreases remarkably, despite the slight reduction of gate voltage diffusion (compared with that of the subthreshold). These results have been interpreted by using previously reported models for threshold current variability, load displacement, and simple analytical calculations. Scaling analysis shows that the variability of the characteristics of this semiconductor increases as the effects of the short channel increases. Therefore, with a slight increase of length and a reduction of width, oxide thickness, and dopant factor, we could correct the effect of the short channel.     

High-voltage and low specific on-resistance power UMOSFET using P and N type columns

For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10 µm drift region length the maximum breakdown voltage of 1274 V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703 V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (R_on,sp) of 2 mΩ cm², which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively.