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一种堆栈型Java处理器的流水线设计
引用本文:杨骥,毛峡.一种堆栈型Java处理器的流水线设计[J].计算机工程与设计,2004,25(12):2357-2359.
作者姓名:杨骥  毛峡
作者单位:北京航空航天大学,电子信息工程学院,北京,100083
摘    要:针对目前嵌入式系统的特点,设计了一种四段流水线的堆栈型Java微处理器核。使用双口RAM作为Java栈,减小了存储资源的消耗。通过硬件在一个时钟周期内直接执行Java虚拟机(JVM)中大多数简单的算术/逻辑指令;通过微代码模拟在若干时钟周期内完成中等复杂指令处理;提供硬件陷阱机制,以支持JVM中非常复杂和面向对象指令的软件仿真。综合硬件资源和运行效率两方面的需求可灵活选择不同的指令实现方式,为Java处理器在FPGA中的移植实现提供方便。

关 键 词:堆栈  指令  处理器  时钟周期  JVM  流水线  硬件  陷阱  供方  需求
文章编号:1000-7024(2004)12-2357-03

Pipeline design of stack-based java processor
YANG Ji,MAO Xia.Pipeline design of stack-based java processor[J].Computer Engineering and Design,2004,25(12):2357-2359.
Authors:YANG Ji  MAO Xia
Abstract:The design of JP-01 is a stack-based 4-stage pipelined Java microprocessor core, which is fit for embedded system usage. This microprocessor uses dual-port RAM as java stack memory, which reduces the consumption of memory resource. It can execute most of simple java virtual machine (JVM) arithmetic/logic instructions in one clock period in hardware. It can execute complicated instructions in several clock period by using micro-code ROM. The hardware trap mechanism is provided to simulate the more complicated and object oriented instructions use software. Different implemented can be selected methods for the same JVM instructions on the demand between higher performance and less hardware cost, which is an important factor to implement the design into FPGA.
Keywords:java  microprocessor  pipeline
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