Buried source-side injection (BSSI) for flash EPROM programming

A flash-EPROM cell structure that can be programmed at low drain voltages and low power is disclosed. The new element in the device structure is the incorporation of buried junction at the source side where the high electric field region is established during programming. The cell is programmed by hot-electron injection at the source side and erased by Fowler-Nordheim tunneling at the drain side. Typical programming time of 10 μs/byte can be accomplished with 3.5 V on the drain junction. The structure can be built with the standard EPROM technology and can offer advantages in low-voltage power supply systems such as portable and notebook computers     

The promising multi-bit/level programming operations for nano-scaled SONOS memory

In order to obtain a reliable multi-bit/level operation for nano-scaled polycrystalline silicon-oxide-nitride-oxide-silicon (SONOS) memory, two different localized charge-injection programming methods, the channel hot electron injection with a positive substrate bias (CHEI-P) and pulse agitated substrate hot electron injection (PASHEI), are operated in 90 nm SONOS cells. It is found that the cells programmed by CHEI-P have the better endurance property than by PASHEI. The better endurance is due to the less accumulation of charges in the nitride layer, evidenced by surface potential profiling technique. CHEI-P program further exhibits the superior endurance and retention properties after 10⁴ program/erase cycles in 4-bit/4-level operations. These results illustrate that CHEI-P program is a promising candidate for multi-bit/levels nano-sized SONOS memory.     

A novel SONOS nonvolatile flash memory device using substrate hot-hole injection for write and gate tunneling for erase

In this work, we describe a novel SONOS device suitable for future nonvolatile flash memories. Substrate hot-hole injection (HHI) through a bottom oxide is used for write and gate tunneling through a thin top oxide is employed for erase. We present device DC and dynamic characteristics at low voltages (<10 V) for SONOS devices with a gate dielectric stack consisting of a 3.8 nm bottom oxide, 1.5 nm nitride and 3.0 nm top oxide. We obtain a reduction in power consumption by 4 orders of magnitude, an improvement in retention by 90%, and an improvement in subthreshold swing by 40% with a novel write/erase technique compared with Substrate HHI for erase and channel hot electron (CHE) injection for write.     

An analytical programming model for the drain-coupling source-side injection split gate flash EEPROM

This paper presents a compact and accurate analytical model for evaluating the programming behaviors of the drain-coupling source-side injection (SSI) split-gate Flash memory. Starting with the bias-dependent and time-varying drain coupling ratio, a programming model is developed on the basis of the constant barrier height approximation and Lucky-electron model to express the full transient injection current, peak lateral electric field, and storage charge as functions of technological, physical, and electrical parameters. The extracted re-direction mean-free path of the SSI device is smaller than that of the channel hot-electron counterpart by one order of magnitude, which provides the physical intuition for the derived high injection efficiency of around 2/1000. The intrinsic coupling ratio depends only on technological parameters and is presented as the design index of the device. The usefulness of this model is its ability of constructing the complete operation plot of the time-to-program versus the programming voltage for various reliability windows and tunable technological parameters. Besides, the variance of the read current distribution of a memory array is also analytically predicted.     

A novel method to improve cell endurance window in source-side injection split gate flash memory

To enhance cell endurance window of a split gate flash memory, we used a ramp pulse with long rising time to replace the conventional square pulse for programming. The change is based on the study of the electric field at electron injection point (E_G) related to programming time. Statistic measurements on various samples including different technologies, cell locations (even or odd) and rise times were done. The results confirm that the read currents shift under erase state (ΔI_r1) could be improved significantly with an acceptable programming speed by the proposed method.For example, as increasing the rising time from 0.1 μs to 20 μs for the conventional square pulse and the ramp pulse respectively, after 1 M cycling the ΔI_r1 is reduced from 64.8% to 36.2% with an acceptable minimum programming time of 12.5 μs.     

An 8-level 3-bit cell programming technique in NOR-type nano-scaled SONOS memory devices

An 8-level 3-bit cell programming technique is presented in NOR-type nano-scaled polycrystalline silicon-oxide–nitride-oxide-silicon (SONOS) memory devices. This new operating mode provides the double programming and sensing window over the traditional 4-level cell programming by using a double-side hot hole injection erasing. Compared with the 4-level cell, the storage density of the 8-level cell is greatly improved. However, the cycling endurance and retention properties are not obviously degraded until 1000 program/erase cycling.     

Impact of gate-to-source/drain misalignments on source-side injection Schottky barrier charge-trapping memory cells evaluated using numerical programming-trapping iterations

This work numerically elucidates the effects of gate-to-source/drain misalignments on source-side injection Schottky barrier charge-trapping memory cells. The coupling of Schottky barriers and trap charges generate particular Schottky barrier lowering and source-side injection, while the charge-coupled Schottky barriers must be considered concurrently with the precise positions of metallic source/drain junctions. Numerical programming-trapping iterations were employed to examine the distribution of electron injections and trapped charges in the charge-coupled cells, and to discuss the differences of physical mechanisms among the aligned, overlapped, and underlapped cells. The overlapped cells produce a mildly high programming and reading currents because of the shorter effective lengths. However, the underlapped cells suffer severely from the degradation of electron drain current, hot-carriers injection, and threshold-voltage shift because of widened tunneling barrier, reduced electric field, and invalid injection location. Mildly gate-to-source/drain overlap should be designed in Schottky barrier charge-trapping memories to avoid the underlapped offsets, ensuring favorable programming and reading performance.     

A source-side injection erasable programmable read-only-memory (SI-EPROM) device

A new erasable programmable read-only memory (EPROM) device with promise for low-voltage high-speed programming is described. This device is an asymmetrical n-channel stacked-gate MOSFET, with a short weak gate-control channel region introduced close to the source. At high gate bias, a strong channel electric field is created in this local region even at a relatively low drain voltage. Furthermore, the gate oxide field in this region also aids the injection of hot electrons into the floating gate. As a result, the source-side injection EPROM (SI-EPROM) has shown 10-µs programming speed at a drain voltage of 5 V.     

A new and flexible scheme for hot-electron programming ofnonvolatile memory cells

A new hot electron writing scheme for flash EEPROMs is proposed that combines a positive source to bulk voltage and a ramped voltage on the control gate. The scheme exploits the equilibrium between hot electron injection and displacement current at the floating gate electrode in order to achieve a transient regime where the drain current of the cell is virtually constant. The new method allows one to accurately control the threshold voltage and the programming drain current that is essentially determined by the slope of the control gate ramp and can thus be traded off with programming time over a wide range of values. The main features of the new scheme are experimentally demonstrated on up-to-date 0.6 μm stacked gate flash EEPROM devices     

A single-sided PHINES SONOS memory featuring high-speed and low-power applications

A single-sided PHINES SONOS memory with hot-hole injection in program operation and Fowler-Nordheim (FN) tunneling in erase operation has been demonstrated for high program speed and low power applications. High programming speed (/spl Delta/V/sub t//program time) of 5 V/20 /spl mu/s, low power consumption of P/E, high endurance of 10 K, good retention, and scaling capability can be demonstrated.     

Scaling of multidielectric nonvolatile SONOS memory structures

Present-day low-power, portable lap-top computers and consumer products require non-volatile semiconductor memory (NVSM) operating at 5 V with a trend towards reducing this level to 3.3 V. The SONOS technology, an acronym for the polySilicon-blocking Oxide-Nitride-tunnel Oxide-Silicon structure used in capacitors and transistors, shows promise as a technology for present and future low voltage NVSM applications. The nitride layer in the dielectric sandwich permits the storage of charge resulting in adjustable threshold voltages. This paper examines the physics and characterization of scaled SONOS NVSM transistors in relation to reducing the programming voltage. We develop a model for the transient characteristics of the SONOS NVSM transistor with: (1) a simple closed-form solution valid for short programming times; and (2) a numerical solution covering the entire range of programming times. The simple closed-form solution clearly illustrates the dependence of the turn-on time and erase/white slope on the dielectric thicknesses, initial stored charge in the nitride, and programming voltage. In particular, we have examined: (1) decreasing the tunnel oxide thickness; and (2) scaling the blocking oxide thickness. By properly scaling the dielectric films (11 Å tunnel oxide, 50 Å nitride, 40 Å blocking oxide), a ±8 V programmable SONOS device has been obtained with a 50 μs write time and a 100 μs erase time for a 3 V memory window, and a ±5 V programmable device with a 100 ms erase and write time for a 1.5 V memory window.     

Lateral profiling of trapped charge in SONOS flash EEPROMs programmed using CHE injection

The lateral profile of trapped charge in a silicon-oxide-nitride-oxide-silicon (SONOS) electrically erasable programmable read-only memory programmed using channel-hot-electron injection is determined using current-voltage (I/sub D/-V/sub G/) measurements along with two-dimensional device simulations and is verified using gate-induced-drain-leakage measurements, charge-pumping (CP) measurements, and Monte Carlo simulations. An iterative procedure is used to match simulated I/sub D/-V/sub G/ characteristics with experimental I/sub D/-V/sub G/ characteristics at different stages of programming, by sequentially increasing the trapped electron charge in simulations. Fresh cells are found to contain a high laterally nonuniform trapped charge, which (along with large electron injection during the program) make the conventional CP techniques inadequate for extracting the charge profile. This charge results in a nonmonotonous variation of threshold and flat-band voltages along the channel and makes it impossible to simultaneously determine interface and trapped charge profiles using CP alone. The CP technique is modified for application to SONOS cells and is used to verify the charge profile obtained using I/sub D/-V/sub G/ and to estimate the interface degradation. This paper enhances the study presented in our earlier work.     

A new transit-time device using quantum-well injection

The use of such techniques as molecular beam epitaxy has allowed the fabrication of devices in which tunneling is the dominant transport mechanism. In this paper a new transit-time device which uses resonant tunneling through a quantum well is proposed and analyzed. Depending on the bias level, this device may permit injection of carriers into the drift region at more favorable phase angles (hence higher efficiencies) than other transit-time devices. The device promises low noise performance and should be capable of operating at high millimeter-wave frequencies with higher output power than other transit-time devices or pure quantum-well oscillators. Since the device uses quantum-well injection and transit-time effects, it is called a QWITT diode.     

Nonvolatile floating-gate memory programming enhancement using well bias

A nonvolatile memory programming approach using ohmic and Schottky well bias contacts is proposed. Programming efficiency using positive and negative bias voltages are compared in addition to electric field differences between the biases and type of contacts using experimental data and simulations. High-injection efficiency of electrons to the floating-gate is achieved using a negatively biased Schottky contact and a positively biased ohmic contact. A low-injection efficiency is achieved using a negatively biased ohmic contact and a positively biased Schottky contact.     

A new combination-erase technique for erasing nitride based (SONOS) nonvolatile memories

A new technique of erasing nonvolatile memory (NVM) devices based on nitride storage (SONOS) with bottom oxide thickness in the range of 30 /spl Aring/ has been developed. Oxide thickness in this range is necessary to minimize the undesirable effects of gate disturb while still enabling a low-voltage operation to maximize the cost benefit of SONOS memories. To erase such bitcells, Fowler-Nordheim tunneling (FNT) is preferred over hot-hole injection (HHI) due to the less damaging nature of FNT. However, FNT alone cannot be used to erase the device completely due to erase saturation limitations. Hence, the new "combination-erase" technique combines both FNT and HHI erase to achieve a fast and controlled erase. Furthermore, by using FNT erase at higher field conditions, and HHI erase at lower field conditions, the reliability of the bitcell is also improved.     

Performance improvement of SONOS memory by bandgap engineering of charge-trapping layer

A significant improvement in device performance and reliability characteristics of silicon-oxide-nitride-oxide-silicon (SONOS) Flash memory has been achieved. Superior endurance characteristic shows no sign of degradation even after 10/sup 6/ program/erase cycles and an extrapolated ten-year detection window of 1.4 V has been attained from retention measurement. The dramatic improvement results from a bandgap engineering of the SiN charge-trapping layer. With a gradual variation of the Si/N ratio from bottom to top of nitride film rather than uniform standard composition, a large number of highly accessible trapping levels are created in addition to the deepened barrier height between nitride and tunnel oxide that reduces back-tunneling probability. The proposed technique shall be valuable in pushing Flash memory technology into the next generation.