用正向栅控二极管的方法对场效应晶体管的参数提取

本文用正向栅控二极管的方法来提取场效应晶体管的栅氧层厚度和体掺杂浓度,尤其是在这两个变量事先都未知的情况下进行提取。首先,用器件物理推导出了以栅氧层厚度、体掺杂浓度为参数的正向栅控二极管峰值电流。然后用ISE-Dessis模拟了不同栅氧层厚度和体衬底掺杂浓度下的产生复合电流峰值的特性,用于参数提取。模拟数据的结果与正向栅控二极管的方法显示出高度的一致性。     

栅控二极管R-G电流法表征SOI-MOS器件埋氧层界面陷阱的敏感性分析

通过数值模拟手段,用归一化的方法研究了界面陷阱、硅膜厚度和沟道掺杂浓度对R-G电流大小的影响规律.结果表明:无论在FD还是在PD SOI MOS器件中,界面陷阱密度是决定R-G电流峰值的主要因素,硅膜厚度和沟道掺杂浓度的影响却因器件的类型而异.为了精确地用R-G电流峰值确定界面陷阱的大小,器件参数的影响也必须包括在模型之中.     

栅控二极管正向R-G电流对SOI体陷阱特征和硅膜结构的依赖性

使用半导体器件数值分析工具DESSISE-ISE,对侧向的P＋P－N＋栅控二极管的正向R-G电流对SOI体陷阱特征和硅膜结构的依赖性进行了详尽的研究．通过系统地改变硅膜体陷阱的密度和能级分布,得出了相应的P＋P－N＋栅控二极管的正向R-G电流的变化．同时,表征硅膜结构的参数如沟道掺杂和硅膜厚度的变化也使器件从部分耗尽向全耗尽方向转化,分析了这种转化对R-G电流大小和分布的影响．     

FORWARD GATED-DIODE R-G CURRENT METHOD:A SIMPLE NOVEL TECHNIQUE FOR CHARACTERIZING LATERAL LIGHTLY DOPING REGION OF LDD MOSFET's

This paper presents a simple novel technique-forward gated-diode R-G current method-to determine the lateral lightly-doped source/drain (S/D) region interface state density and effective surface doping concentration of the lightly-doped drain (LDD) N- MOSFET's simultaneously. One interesting result of the numerical analysis is the direct characterization of the interface state density and characteristic gate voltage values corresponding to LDD effective surface doping concentration. It is observed that the S/D N- surface doping concentration and corresponding region's interface state density are R-G current peak position and amplitude dependent, respectively. It is convincible that the proposed method is well suitable for the characterization of deep sub-micron MOSFET's in the current ULSI technology.     

FORWARD GATED—DIODE METHOD FOR EXTRACTING HOT—CARRIER—STRESS0INDUCED BACK INTERFACE TRAPS IN SOI／NMOSFETs

The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method directly gives the induced interface trap density from the measured R-G current peak of the gated-diode architecture. An expected power law relationship between the induced back interface trap density and the accumulated stress time has been obtained.     

FORWARD GATED-DIODE R-G CURRENT METHOD:A SIMPLE NOVEL TECHNIQUE FOR CHARACTERIZING LATERAL LIGHTLY DOPING REGION OF LDD MOSFET’s

 This paper presents a simple novel technique-forward gated-diode R-G current method-to determine the lateral lightly-doped source/drain (S/D) region interface state density and effective surface doping concentration of the lightly-doped drain (LDD) N- MOSFET’s simultaneously. One interesting result of the numerical analysis is the direct characterization of the interface state density and characteristic gate voltage values corresponding to LDD effective surface doping concentration. It is observed that the S/D N- surface doping concentration and corresponding region’s interface state density are R-G current peak position and amplitude dependent, respectively. It is convincible that the proposed method is well suitable for the characterization of deep sub-micron MOSFET’s in the current ULSI technology.     

Clear correspondence between gated-diode R-G current and performance degradation of SOI n-MOSFETs after F-N stress tests

A clear correspondence between the gated-diode generation-recombination (R-G) current and the per-formance degradation of an SOI n-channel MOS transistor after F-N stress tests has been demonstrated. Due to the increase of interface traps after F-N stress tests, the R-G current of the gated-diode in the SOI-MOSFET architecture increases while the performance characteristics of the MOSFET transistor such as the saturation drain current and sub-threshold slope are degraded. From a series of experimental measurements of the gated-diode and SOI-MOSFET DC characteristics, a linear decrease of the drain saturation current and increase of the threshold volt-age as well as a like-line rise of the sub-threshold swing and a corresponding degradation in the trans-conductance are also observed. These results provide theoretical and experimental evidence for us to use the gated-diode tool to monitor SOI-MOSFET degradation.     

新的正向栅控二极管技术分离热载流子应力诱生SOI NMOSFET界面陷阱和界面电荷的研究

报道了用新的正向栅控二极管技术分离热载流子应力诱生的SOI-MOSFET界面陷阱和界面电荷的理论和实验研究.理论分析表明:由于正向栅控二极管界面态R-G电流峰的特征,该峰的幅度正比于热载流子应力诱生的界面陷阱的大小,而该峰的位置的移动正比于热载流子应力诱生的界面电荷密度. 实验结果表明:前沟道的热载流子应力在前栅界面不仅诱生相当数量的界面陷阱,同样产生出很大的界面电荷.对于逐渐上升的累积应力时间,抽取出来的诱生界面陷阱和界面电荷密度呈相近似的幂指数方式增加,指数分别为为0.7 和0.85.     

Drain-avalanche and hole-trapping induced gate leakage inthin-oxide MOS devices

Leakage current components due to band-to-band tunneling and avalanche breakdown in thin-oxide (90-160 Å) gated-diode structures are discussed. Experimental results show that while the band-to-band tunneling current is not sensitive to channel doping concentration, the avalanche current is sensitive to channel doping concentration in the range of 10¹⁶ to 10¹⁷ cm^-3. For oxides thicker than 110 Å, the gate current is found to be dominated by hot-hole injection and for oxides thinner than 110 Å the gate current is dominated by Fowler-Nordheim electron tunneling. After hot-hole injection, the gate oxide exhibits significant low-level leakage, which is explained by the barrier-lowering effect caused by the trapped holes in the oxide     

对称三材料双栅应变硅MOSFET亚阈值电流与亚阈值斜率解析模型

基于泊松方程和边界条件,推导了对称三材料双栅应变硅金属氧化物半导体场效应晶体管（MOSFET：metal oxide semiconductor field effect transistor）的表面势解析解.利用扩散-漂移理论,在亚阈值区电流密度方程的基础上,提出了亚阈值电流与亚阈值斜率二维解析模型.分析了沟道长度、功函数差、弛豫SiGe层的Ge组份、栅介质层的介电常数、应变硅沟道层厚度、栅介质高k层厚度和沟道掺杂浓度等参数对亚阈值性能的影响,并对亚阈值性能改进进行了分析研究.研究结果为优化器件参数提供了有意义的指导.模型解析结果与DESSIS仿真结果吻合较好.     

90nm pMOSFET脱耦等离子体制备氮氧化硅的负偏压温度失稳性(英文)

MOSFET器件继续微缩则闸极氧化层厚度将持续减小,在0.13μm的技术闸极二氧化硅的厚度必须小于2nm,然而如此薄的氧化层直接穿透电流造成了明显的漏电流。为了降低漏电流,二氧化硅导入高浓度的氮如脱耦等离子体氮化制备氮氧化硅受到高度重视。然而,脱耦等离子体氮化制备氮氧化硅的一项顾虑是pMOSFET负偏压温度的失稳性。在此研究里测量了脱耦等离子体氮化制备氮氧化硅pMOSFET负偏压温度失稳性,并且和传统的二氧化硅闸电极比较,厚度1.5nm的脱耦等离子体氮化制备氮氧化硅pMOSFET和厚度1.3nm的二氧化硅pMOSFET经过125℃和10.7MVcm的电场1h的应力下比较阈值电压,结果显示脱耦等离子体氮化制备氮氧化硅pMOSFET在负偏压温度应力下性能较差。在15%阈值电压改变的标准下,延长10年的寿命,其最大工作电压是1.16V,可以符合90nm工艺1V特操作电压的安全范围内。     

Asymmetric gate-induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance

Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations. This paper investigates the effect of the asymmetric source and drain geometries of surround-gate vertical MOSFETs on the drain leakage currents in the OFF-state region of operation. Measurements of gate-induced drain leakage (GIDL) and body leakage are carried out as a function of temperature for transistors connected in the drain-on-top and drain-on-bottom configurations. Asymmetric leakage currents are seen when the source and drain terminals are interchanged, with the GIDL being higher in the drain-on-bottom configuration and the body leakage being higher in the drain-on-top configuration. Band-to-band tunneling is identified as the dominant leakage mechanism for both the GIDL and body leakage from electrical measurements at temperatures ranging from -50 to 200/spl deg/C. The asymmetric body leakage is explained by a difference in body doping concentration at the top and bottom drain-body junctions due to the use of a p-well ion implantation. The asymmetric GIDL is explained by the difference in gate oxide thickness on the vertical <110> pillar sidewalls and the horizontal <100> wafer surface.     

90 nm pMOSFET脱耦等离子体制备氮氧化硅的负偏压温度失稳性

MOSFET器件继续微缩则闸极氧化层厚度将持续减小,在0.13μm的技术闸极二氧化硅的厚度必须小于2 nm,然而如此薄的氧化层直接穿透电流造成了明显的漏电流.为了降低漏电流,二氧化硅导入高浓度的氮如脱耦等离子体氮化制备氮氧化硅受到高度重视.然而,脱耦等离子体氮化制备氮氧化硅的一项顾虑是pMOSFET负偏压温度的失稳性.在此研究里测量了脱耦等离子体氮化制备氮氧化硅pMOSFET负偏压温度失稳性,并且和传统的二氧化硅闸电极比较,厚度1.5 nm的脱耦等离子体氮化制备氮氧化硅pMOSFET和厚度1.3 nm的二氧化硅pMOSFET经过125℃和10.7MV/cm的电场1 h的应力下比较阈值电压,结果显示脱耦等离子体氮化制备氮氧化硅pMOSFET在负偏压温度应力下性能较差.在15%阈值电压改变的标准下,延长10年的寿命,其最大工作电压是1.16 V,可以符合90 nm工艺1 V特操作电压的安全范围内.     

High-current snapback characteristics of MOSFETs

The high-current snapback characteristics of MOSFETs with different channel lengths and widths, gate oxide thicknesses, and substrate dopings were studied to determine their effectiveness in electrostatic discharge stress protection. Filamentary conduction was not observed for currents up to 7 mA/μm of channel width for a pulsewidth of 500 ns. MOSFETs with shorter channel lengths require lower voltages to sustain the same current, independent of gate oxide thickness. Increasing the substrate doping does not necessarily reduce the high current voltage. These trends can be explained using a simple lateral n-p-n bipolar transistor snapback model     

一种新的Halo掺杂圆柱围栅MOSFET阈值电压解析模型

通过在圆柱坐标系中精确求解泊松方程,建立了全新的Halo掺杂圆柱围栅MOSFET静电势,电场以及阈值电压的解析模型。与采用抛物线电势近似法得到的解析模型相比,当沟道半径远大于氧化层厚度时,新模型更为精确。模型还考虑了Halo区掺杂浓度、氧化层厚度以及沟道半径对器件阈值电压特性的影响。结果表明,采用中等程度的halo区掺杂浓度、较薄的栅氧化层以及较小的沟道半径可以有效改善器件的阈值电压特性。解析模型与三维数值模拟软件ISE所得结果高度吻合。     

Ge n-MOSFETs on lightly doped substrates with high-/spl kappa/ dielectric and TaN gate

In this letter, we report successful fabrication of germanium n-MOSFETs on lightly doped Ge substrates with a thin HfO/sub 2/ dielectric (equivalent oxide thickness /spl sim/10.8 /spl Aring/) and TaN gate electrode. The highest peak mobility (330 cm/sup 2//V/spl middot/s) and saturated drive current (130 /spl mu/A/sq at V/sub g/--V/sub t/=1.5 V) have been demonstrated for n-channel bulk Ge MOSFETs with an ultrathin dielectric. As compared to Si control devices, 2.5/spl times/ enhancement of peak mobility has been achieved. The poor performance of Ge n-MOSFET devices reported recently and its mechanism have been investigated. Impurity induced structural defects are believed to be responsible for the severe degradation.     

Experimental and theoretical investigations on short-channel effects in 4H-SiC MOSFETs

In this paper, a fundamental investigation on short-channel effects (SCEs) in 4H-SiC MOSFETs is given. Planar MOSFETs with various channel lengths have been fabricated on p-type 4H-SiC (0001), (0001) and (1120) faces. In the fabricated MOSFETs, SCEs such as punchthrough behavior, decrease of threshold voltage, deterioration of subthreshold characteristics, and saturation of transconductance occur by reducing channel length. The critical channel lengths below which SCEs occur are analyzed as a function of p-body doping and oxide thickness by using device simulation. The critical channel lengths obtained from the device simulation is in good agreement with the empirical relationship for Si MOSFETs. The critical channel lengths in the fabricated SiC MOSFETs are slightly longer than simulation results. The dependence of crystal face orientations on SCEs is hardly observed. Impacts of interface charge on the appearance of SCEs are discussed.     

Hot carrier degradation of n-channel MOSFETs characterized by agated-diode measurement technique

The gated-diode measurement technique characterizes the physical damage induced in n-channel MOSFETs during hot-carrier stress. The results show that the gate oxide in the channel region is not affected by hot-carrier stress. The most severe damage is located in the gate oxide above the drain-gate overlap region. Furthermore, the measurements show that the density of generation centers in the substrate is increased after hot-carrier stress     

倒掺杂沟道MOSFETs的研究

本文研究了一种倒掺杂沟道MOSFET。与传统的MOSFETs不同,这种器件采用沟道表面掺杂浓度低、体内掺杂浓度高的倒掺杂设计。基于Possion方程,建立了线性变掺杂的沟道倒掺杂模型,得出了器件表面电势以及漏极电流的表达式,研究了垂直于沟道方向上倒掺杂的陡峭程度对漏极电流、饱和驱动电流以及表面电势的影响。计算结果与二维仿真软件MEDICI模拟结果相符。     

长沟道圆柱围栅高K栅栈结构MOSFETs器件的直接隧穿电流解析模型

An analytical direct tunneling gate current model for cylindrical surrounding gate（CSG） MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate＇s oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current.Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.