GeSiMOSFET的纵向结构对器件性能的影响

为了研究器件参数对GeSi MOSFET器件性能的影响,本文在建立一个简单的GeSi MOSFET的器件模型的基础上,对GeSi MOSFET的纵向结构进行了系统的理论分析.确定了纵向结构的CAP层厚度、沟道层载流子面密度、DELTA掺杂浓度以及量子阱阱深之间的关系,得出了阈值电压与DELTA掺杂浓度、栅氧化层厚度及CAP层厚度之间的关系,还得出了栅压与沟道载流子面密度、栅氧化层厚度及CAP层厚度之间的关系.并且在此基础上得出了一些有意义的结果.为了更细致、精确地进行分析,我们分别对GeSi PMOSFET和GeSi NMOSFET在MEDICI上做了模拟.     

应变Si调制掺杂NMOSFET电子面密度模型

应变Si(Strain Si)调制掺杂NMOSFET量子阱沟道中电子面密度直接影响器件的开关特性.本文通过求解泊松方程,建立了应变Si调制掺杂NMOSFET量子阱沟道静态电子面密度模型,并据此建立了器件阈值电压模型,利用MATLAB软件对该模型进行了数值分析.讨论了器件结构中δ-掺杂层杂质浓度和间隔层厚度与电子面密度和阈值电压的关系,分析了器件几何结构参数和材料物理参数对器件量子阱沟道静态电子面密度和阈值电压的影响.随着δ-掺杂层杂质浓度的减小和间隔层厚度的增加,量子阱沟道中电子面密度减小,阈值电压绝对值减小.     

pMOS器件NBTI效应随着器件参数变化规律的一种模型

器件的负偏压温度不稳定性(Negative bias temperature instability,NBTI)退化依赖于栅氧化层中电场的大小和强反型时沟道空穴浓度,沟道掺杂浓度的不同显然会引起栅氧化层电场的变化。栅氧化层的厚度不仅影响栅氧化层电场,而且会影响沟道空穴浓度,因而,改变沟道掺杂浓度和栅氧化层厚度会引起NBTI退化的不同。首先利用pMOSFETS器件的能带图和NBTI的退化模型,推导出了器件NBTI随器件参数变化的公式,并修订了NBTI的数值模拟方法,然后分别利用理论计算和数值模拟的方法对不同器件参数、相同阈值电压的器件进行定量地计算和仿真,继而总结出一种分析器件NBTI退化的应用模型,可对集成电路和器件的可靠性设计提供指导。     

非均匀沟道DMOS器件阈值电压模型

提出了DMOS器件的二维电荷阈值电压模型。基于沟道区杂质的二维分布,求解泊松方 程,得到沟道区中耗尽电荷总量,给出DMOS二维阈值电压模型的解析式。该模型的解析解与实验 结果和数值解相吻合。并对DMOS的短沟效应和阈值电压与沟道表面扩散浓度、沟道结深和沟道 长度等参数的关系进行了深入分析,给出了短沟DMOS器件阈值电压的解析式。文中还给出了沟 道表面掺杂浓度在2.0×1016cm-3到10.0×1016cm-3范围内DMOS器件的阈值电压简明计算式。该 模型解决了习用的DMOS器件阈值电压模型解析值比实验结果大100％以上的问题。     

异质栅非对称Halo SOI MOSFET

为了抑制异质栅SOI MOSFET的漏致势垒降低效应,在沟道源端一侧引入了高掺杂Halo结构.通过求解二维电势Poisson方程,为新结构器件建立了全耗尽条件下表面势和阈值电压解析模型,并对其性能改进情况进行了研究.结果表明,新结构器件比传统的异质栅SOI MOSFETs能更有效地抑制漏致势垒降低效应,并进一步提高载流子输运效率.新结构器件的漏致势垒降低效应随着Halo区掺杂浓度的增加而减弱,但随Halo区长度非单调变化.解析模型与数值模拟软件MEDICI所得结果高度吻合.     

异质栅非对称Halo SOI MOSFET

为了抑制异质栅SOI MOSFET的漏致势垒降低效应，在沟道源端一侧引入了高掺杂Halo结构．通过求解二维电势Poisson方程，为新结构器件建立了全耗尽条件下表面势和阈值电压解析模型，并对其性能改进情况进行了研究．结果表明，新结构器件比传统的异质栅SOI MOSFETs能更有效地抑制漏致势垒降低效应，并进一步提高载流子输运效率．新结构器件的漏致势垒降低效应随着Halo区掺杂浓度的增加而减弱，但随Halo区长度非单调变化．解析模型与数值模拟软件MEDICI所得结果高度吻合．     

全耗尽SOI MOSFETs阈值电压解析模型

提出了一种新的全耗尽SOI MOSFETs阈值电压二维解析模型.通过求解二维泊松方程得到器件有源层的二维电势分布函数,氧化层-硅界面处的电势最小值用于监测SOI MOSFETs的阈值电压.通过对不同栅长、栅氧厚度、硅膜厚度和沟道掺杂浓度的SOI MOSFETs的MEDICI模拟结果的比较,验证了该模型,并取得了很好的一致性.     

An Analytical Threshold Voltage Model for Fully Depleted SOI MOSFETs

提出了一种新的全耗尽SOI MOSFETs阈值电压二维解析模型.通过求解二维泊松方程得到器件有源层的二维电势分布函数,氧化层-硅界面处的电势最小值用于监测SOI MOSFETs的阈值电压.通过对不同栅长、栅氧厚度、硅膜厚度和沟道掺杂浓度的SOI MOSFETs的MEDICI模拟结果的比较,验证了该模型,并取得了很好的一致性.     

声电输运器件的沟道特性研究

为实现砷化镓声电输运,必须在外延层中建立电子输运沟道.本文对金属-n型外延层-半绝缘衬底结构的输运沟道给出耗尽分析的解析表达式,分析了外延层厚度、掺杂浓度、偏置电压等参数对输运沟道耗尽特性的影响,以及器件表面存在氧化层时对器件工作特性的影响.     

非对称HALO结构的全耗尽SOI二维阈值电压解析模型

在考虑了隐埋层与硅层的二维效应的基础上提出非对称HALO结构的全耗尽SOI二维阈值电压解析模型,该模型计算了在不同硅膜厚度,掺杂浓度,HALO区占沟道比例的条件下的阈值电压.模型结果与二维数值模拟软件MEDICI的模拟结果较好的吻合,该模型对HALO结构的物理特性和工艺设计有很好的指导意义.     

New analytical threshold voltage model for halo-doped cylindrical surrounding-gate MOSFETs

Using an exact solution of two-dimensional Poisson’s equation in cylindrical coordinates,a new analytical model comprising electrostatic potential,electric field,threshold voltage and subthreshold current for halodoped surrounding-gate MOSFETs is developed.It is found that a new analytical model exhibits higher accuracy than that based on parabolic potential approximation when the thickness of the silicon channel is much larger than that of the oxide.It is also revealed that moderate halo doping concentration,thin gate oxide thickness and small silicon channel radius are needed to improve the threshold voltage characteristics.The derived analytical model agrees well with a three-dimensional numerical device simulator ISE.     

全耗尽SOI LDMOS阈值电压的解析模型

通过准二维的方法,求出了全耗尽SOILDMOS晶体管沟道耗尽区电势分布的表达式,并建立了相应的阈值电压模型。将计算结果与二维半导体器件模拟软件MEDICI的模拟结果相比较,两者误差较小,证明了本模型的正确性。从模型中可以容易地分析阈值电压与沟道浓度、长度、SOI硅膜层厚度以及栅氧化层厚度的关系,并且发现ΔVth与背栅压的大小无关。     

Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2.     

A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs

A compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs has been derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included. The new model is verified by published numerical simulations with close agreement. Applying the newly developed model, threshold voltage sensitivities to channel length, channel thickness, and gate oxide thickness have been comprehensively investigated. For practical device designs the channel length causes 30-50% more threshold voltage variation than does the channel thickness for the same process tolerance, while the gate oxide thickness causes the least, relatively insignificant threshold voltage variation. Model predictions indicate that individual DG MOSFETs with good turn-off behavior are feasible at 10 nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires development of novel technologies for significant improvement in process control.     

Analytical threshold voltage model for cylindrical surrounding-gate MOSFET with electrically induced source/drain extensions

Physics-based analytical threshold voltage model for cylindrical surrounding-gate MOSFET with electrically induced source/drain extensions is presented. The effect of inversion carriers on the channel’s potential is considered in presented model. Using this analytical model, the characteristics of EJ-CSG are investigated in terms of surface potential and electric field distribution, threshold voltage roll-off, and DIBL. Results show that the application of electrically induced S/D extensions to the cylindrical surrounding-gate MOSFET will successfully suppress the hot-carrier effects, threshold voltage roll-off, and DIBL. It is also revealed that a moderate side-gate bias voltage, a small gate oxide thickness, and a small silicon channel radius are needed to improve device characteristics. The derived analytical model is verified by its good agreement with the three-dimensional numerical device simulator ISE.     

Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs

A two-dimensional (2-D) analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs). Our model includes the effects of the source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide and also the silicon thin film. We demonstrate that the surface potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed SCEs like the hot-carrier effect and drain-induced barrier-lowering (DIBL). The model is extended to find an expression for the threshold voltage in the submicrometer regime, which predicts a desirable "rollup" in the threshold voltage with decreasing channel lengths. The accuracy of the results obtained using our analytical model is verified using 2-D numerical simulations.     

Semi-Analytical Modeling of Short-Channel Effects in Si and Ge Symmetrical Double-Gate MOSFETs

A simple analytical expression of the 2-D potential distribution along the channel of silicon symmetrical double-gate (DG) MOSFETs in weak inversion is derived. The analytical solution of the potential distribution is compared with the numerical solution of the 2-D Poisson's equation in terms of the channel length L, the silicon thickness t _Si, and the gate oxide thickness t _OX. The obtained results show that the analytical solution describes, with good accuracy, the potential distribution along the channel at different positions from the gate interfaces for well-designed devices when the ratio of L/t _Si is ges 2-3. Based on the 2-D extra potential induced in the silicon film due to short-channel effects (SCEs), a semi-analytical expression for the subthreshold drain current of short-channel devices is derived. From the obtained subthreshold characteristics, the extracted device parameters of the subthreshold slope, drain-induced barrier lowering, and threshold voltage are discussed. Application of the proposed model to devices with silicon replaced by germanium demonstrates that the germanium DG MOSFETs are more prone to SCEs.     

Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

In this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters.     

SiGe沟道pMOSFET阈值电压模型

通过求解泊松方程,综合考虑短沟道效应和漏致势垒降低效应,建立了小尺寸S iG e沟道pM O SFET阈值电压模型,模拟结果和实验数据吻合良好。模拟分析表明,当S iG e沟道长度小于200 nm时,阈值电压受沟道长度、G e组份、衬底掺杂浓度、盖帽层厚度、栅氧化层厚度的影响较大。而对于500 nm以上的沟道长度,可忽略短沟道效应和漏致势垒降低效应对阈值电压的影响。     

双栅和环栅MOSFET中短沟效应引起的阈值电压下降

基于电荷分享原理 ,推导了双栅和环栅 MOSFET短沟效应引起的阈值电压下降 ,分析了衬底掺杂浓度、栅氧化层厚度及硅膜厚度等因素对阈值电压下降的影响 ,并用数值模拟验证了理论结果 .这些研究结果对进一步开展纳米 CMOS新器件的研究有很好的参考价值和实际意义