共查询到16条相似文献,搜索用时 117 毫秒
1.
一种能够抑制部分耗尽SOI nMOSFET浮体效应的新型Schottkty体接触结构的模拟 总被引:1,自引:0,他引:1
提出了一种新型的Schottky体接触结构,能够有效抑制部分耗尽SOI nMOSFET的浮体效应.这种结构可以通过在源区形成一个浅的n+-p结和二次侧墙,然后生长厚的硅化物以穿透这个浅结的方法来实现.模拟结果表明这种结构能够成功抑制SOI nMOSFET中存在的反常亚阈值斜率和kink效应,漏端击穿电压也有显著提高.这种抑制浮体效应的方法不增加器件面积,而且与体硅MOSFET工艺完全兼容. 相似文献
2.
一种能够抑制部分耗尽SOI nMOSFET浮体效应的新型Schottkty体接触结构的模拟 总被引:5,自引:3,他引:2
提出了一种新型的Schottky体接触结构,能够有效抑制部分耗尽SOI nMOSFET的浮体效应.这种结构可以通过在源区形成一个浅的n+-p结和二次侧墙,然后生长厚的硅化物以穿透这个浅结的方法来实现.模拟结果表明这种结构能够成功抑制SOI nMOSFET中存在的反常亚阈值斜率和kink效应,漏端击穿电压也有显著提高.这种抑制浮体效应的方法不增加器件面积,而且与体硅MOSFET工艺完全兼容. 相似文献
3.
提出了一种新型的Schottky体接触结构 ,能够有效抑制部分耗尽SOInMOSFET的浮体效应 .这种结构可以通过在源区形成一个浅的n+ p结和二次侧墙 ,然后生长厚的硅化物以穿透这个浅结的方法来实现 .模拟结果表明这种结构能够成功抑制SOInMOSFET中存在的反常亚阈值斜率和kink效应 ,漏端击穿电压也有显著提高 .这种抑制浮体效应的方法不增加器件面积 ,而且与体硅MOSFET工艺完全兼容 . 相似文献
4.
5.
提高SOI器件和电路性能的研究 总被引:1,自引:0,他引:1
在分析SOI器件的浮体效应、击穿特性、背栅阈值、边缘漏电、ESD及抗辐照特性的基础上,提出了提高SOI器件和电路性能的技术途径.体接触是防止浮体效应的最好方法;正沟道和背沟道的BF2/B离子注入可以分别满足阈值和防止背栅开启的需要;SOI器件栅电极的选取严重影响器件的性能;源区的浅结有助于减小寄生npn双极晶体管的电流增益;而自对准硅化物技术为SOI器件优良特性的展现发挥了重要作用.研究发现,采用综合加固技术的nMOS器件,抗总剂量的水平可达1×106rad(Si). 相似文献
6.
在分析SOI器件的浮体效应、击穿特性、背栅阈值、边缘漏电、ESD及抗辐照特性的基础上,提出了提高SOI器件和电路性能的技术途径. 体接触是防止浮体效应的最好方法;正沟道和背沟道的BF2/B离子注入可以分别满足阈值和防止背栅开启的需要;SOI器件栅电极的选取严重影响器件的性能; 源区的浅结有助于减小寄生npn双极晶体管的电流增益;而自对准硅化物技术为SOI器件优良特性的展现发挥了重要作用. 研究发现,采用综合加固技术的nMOS器件,抗总剂量的水平可达1E6rad(Si). 相似文献
7.
在分析SOI器件的浮体效应、击穿特性、背栅阈值、边缘漏电、ESD及抗辐照特性的基础上,提出了提高SOI器件和电路性能的技术途径.体接触是防止浮体效应的最好方法;正沟道和背沟道的BF2/B离子注入可以分别满足阈值和防止背栅开启的需要;SOI器件栅电极的选取严重影响器件的性能;源区的浅结有助于减小寄生npn双极晶体管的电流增益;而自对准硅化物技术为SOI器件优良特性的展现发挥了重要作用.研究发现,采用综合加固技术的nMOS器件,抗总剂量的水平可达1×106rad(Si). 相似文献
8.
9.
10.
11.
Yo-Hwan Koh Jin-Hyeok Choi Myung-Hee Nam Ji-Woon Yang 《Electron Device Letters, IEEE》1997,18(3):102-104
A new SOI MOSFET structure to reduce the floating body effect is proposed and successfully demonstrated. The key idea of the proposed structure is that the field oxide does not consume the silicon film completely, so that the well contact can suppress the body potential increase in SOI MOSFET through the remaining silicon film between the field oxide and buried oxide. The measured results show the suppressed floating body effect as expected. This new structure retains most of the advantages in the propagation delay of the conventional SOI MOSFET without body potential instability. An additional advantage of the proposed structure is that the layout and process are the same as those of bulk CMOS 相似文献
12.
Matsumoto T. Maeda S. Hirano Y. Eikyu K. Yamaguchi Y. Maegawa S. Inuishi M. Nishimura T. 《Electron Devices, IEEE Transactions on》2002,49(1):55-60
We point out for the first time that floating-body effects cause the reduction of the saturation drive current in partially depleted (PD) Sol MOSFETs. It is demonstrated that when the channel concentration of the SOI MOSFETs is set higher in order to suppress the increase of the off current caused by floating-body effects, the drive current decreases due to the large body effect. In the conventional SOI structure where the source-drain junction is in contact with the buried oxide, the 0.18 μm floating PD SOI MOSFET suffers around 17% decrease in the drive current under the same threshold voltage (Vth) in comparison with body-fixed one. However, floating ID SOI MOSFETs show smaller Vth-roll-off. Further considering the short channel effect down to the minimum gate length of 0.16 μm, the current decrease becomes 6%. Also, we propose a floating PD SOI MOSFET with shallow source-drain junction (SSD) structure to suppress the floating-body effects. By using the SSD structure, we confirmed an increase in the drive current 相似文献
13.
Elimination of bipolar induced drain breakdown and singletransistor latch in submicron PD SOI MOSFET
For the first time, we report the combined application of a SiGe source and a delta-doped p+ region in a PD SOI MOSFET to minimize the impact of floating body effect on both the drain breakdown voltage and the single transistor latch. Our results demonstrate that the proposed SOI structure exhibits as large as 200% improvement in the breakdown voltage and is completely immune to single transistor latch when compared to the conventional SOI MOSFET thus improving the reliability of these structures in VLSI applications 相似文献
14.
Kuehne S.C. Chan A.B.Y. Nguyen C.T. Wong S.S. 《Electron Devices, IEEE Transactions on》1998,45(5):1084-1091
Although the buried oxide in the silicon-on-insulator (SOI) MOSFET makes possible higher performance circuits, it is also responsible for various floating body effects, including the kink effect, drain current transients, and history dependence of output characteristics. It is difficult to incorporate an effective contact to the body because of limitations imposed by the SOI structure. One candidate, which maintains device symmetry, is the lateral body contact. However, high lateral body resistance makes the contact effective only in narrow width devices. In this work, a buried lateral body contact in SOI is described which consists of a low-resistance polysilicon strap running under the MOSFET body along the device width. MOSFET's with effective channel length of 0.17 μm have been fabricated incorporating this buried body strap, showing improved breakdown characteristics. Low leakage of the source and drain junctions demonstrates that the buried strap is compatible with deep submicron devices. Device modeling and analysis are used to quantify the effect of strap resistance on device performance. By accounting for the lateral resistance of the body, the model can be used to determine the maximum allowable device width, given the requirement of maintaining an adequate body contact 相似文献
15.
We introduce Silicon/indium arsenide (Si/InAs) source submicron-device structure in order to minimize the impact of floating body effect on both the drain breakdown voltage and single transistor latch in ultra thin SOI MOSFETs. The potential barrier of valence band between source and body reduces by applying the Indium Arsenide (InAs) layer at the source region. Therefore, we can improve the drain breakdown by suppressing the parasitic NPN bipolar device and the hole accumulation in the body. As confirmed by 2D simulation results, the proposed structure provides the excellent performance compared with a conventional SOI MOSFET thus improving the reliability of this structure in VLSI applications. 相似文献
16.
The reduction of drain breakdown voltage in SOI nMOSFETs with floating substrate is related to the presence of a parasitic n-p-n bipolar structure, the base of which is the floating body of the device. reduction of breakdown voltage (compared to the case where a body contact is used) is shown to be dependent on both channel length and minority carrier lifetime in the SOI material. Conversely, it is shown that mere measurement of MOSFET breakdown voltages can be used to extract the minority carrier lifetime in the SOI material.<> 相似文献