应用于AMOLED源极驱动的具有DAC功能的输出缓冲器设计

针对AMOLED驱动芯片小面积、高精度、低功耗的需求,设计了一种具有DAC功能的高性能输出缓冲器。该缓冲器采用轨对轨的输入级和Class AB输出级以适应大的输入输出电压范围,采用Cascode Miller补偿以减小补偿电容大小,其尾电流源可编程以实现4bit DAC功能插值,节约了整体功耗和芯片面积。在UMC80nm CMOS工艺下,仿真结果表明,在0.2～6.3V的输入电压范围内,缓冲器直流增益大于70dB,相位裕度大于60°,静态电流最小可至0.5μA,建立时间低至1.49μs;典型中压3.3V的情况下,直流增益可达129dB,相位裕度为75°,增益带宽为9.4MHz,静态电流为1.3μA;对60mV输入电压进行4bit插值后,输出误差小于0.255mV。设计的缓冲器精度高、建立时间快且功耗低,输出缓冲器实现了第二级DAC的作用,满足了AMOLED源极驱动的应用需求。     

一种应用于AMOLED的宽电压摆幅高精度伽马校正电路设计

针对AMOLED显示驱动芯片对高精度、低功耗的应用需求,设计了一种宽电压摆幅、高精度、具有温度补偿功能的伽马校正电路.电路通过幅值调节和斜率调节,并微调关键点,从而改变DAC输出曲线,更好地拟合灰阶-电压曲线实现高精度.通过使用轨到轨输入级及基于亚阈值跨导恒定设计的输出缓冲器电路保证了宽输入电压范围,采用Cascode...     

一种16位电流舵DAC的高精度前台校准方法

基于28 nm CMOS工艺,采用一种高精度的前台校准技术设计了一款16 bit电流舵数模转换器（Digitalto-analog converter,DAC）电路。该前台校准算法对16 bit数据对应的所有电流源进行校准,并且使用的电流源只有两种大小,降低校准难度的同时也提升了校准的精度。该校准电路引入了两种校准补充电流,分别用于温度和输出电流变化引起电流源失配的补偿,进一步减小了DAC电流源的失配,有效提高了DAC的整体性能。采用校准后,在-40～85℃温度范围内,微分非线性≤0.8 LSB,积分非线性≤2.0 LSB,200 MHz输出信号下无杂散动态范围≥75.3 dB。该校准方法提高了DAC的温度稳定性。     

10-bit TFT-LCD源驱动电路的设计

DAC和驱动Buffer是TFT-LCD源驱动电路芯片中的重要模块,决定着芯片的主要性能。文章讨论了传统的R-DAC结构及其用于10-bit TFT-LCD源驱动电路时的弊端,详细阐述了新型R-DAC+C-DAC的原理以及设计方法,并采用0.35μm 5VCMOS工艺设计和实现了该电路。Hspice仿真结果表明,所设计的DAC电路的DNL和INL分别小于0.4LSB和1.5LSB,输出电压的建立时间小于3.5μs。该新型结构DAC的面积约是传统结构面积的1/8,且能够实现10亿色(210×210×210)的全真彩显示。     

12bit高稳定性数模转换器设计

设计了一款12 bit高稳定性控制类数模转换器(DAC),该DAC集成了带有稳定启动电路的新型低失调带隙基准源(BGR),改善了基准电路的稳定性以及对温度和工艺的敏感性;DAC采用了改进的两级电阻串结构,通过开关电阻匹配和特殊版图布局,在既不增加电路功耗又不扩大版图面积的前提下,提高了DAC的精度并降低了工艺浓度梯度对整体性能的影响.基于CSMC 0.5 μm 5 V 1P4M工艺对所设计的DAC芯片进行了流片验证.测试结果表明:常温下DAC的微分非线性(DNL)小于0.45 LSB,积分非线性(INL)小于1.5 LSB,并且在-55～125℃内DNL小于1 LSB,INL小于2.5 LSB;5V电源电压供电时功耗仅为3.5 mW,实现了高精度、高稳定性的设计目标.     

基于InP DHBT工艺的6 bit DAC设计与实现

基于InP双异质结双极晶体管(DHBT)工艺设计并实现了一款6 bit高速数模转换器(DAC)芯片,该InP工艺DHBT器件的电流增益截止频率大于200 GHz,最高振荡频率大于285 GHz.DAC芯片采用R-2R梯形电阻电流舵结构,输入级采用缓冲预放大器结构,实现输入缓冲及足够高的增益;D触发器单元采用采样/保持两级锁存拓扑结构实现接收数据的时钟同步;采用开关电流源单元及R-2R电阻单元,减小芯片体积,实现高速采样.该DAC最终尺寸为4.5 mmX3.5 mm,功耗为3.5W.实测结果表明,该DAC可以很好地实现10 GHz采样时钟下的斜坡输出,微分非线性为+0.4/-0.24 LSB,积分非线性为+0.61/-0.64 LSB.     

12位数模转换器DAC7311的通信控制及其电流驱动电路设计

采用TI公司的TMS320F28335系列DSP作为主控制器与12bit的数模转换芯片DAC731进行串行通信,通信采用SPI方式。通过CCS软件编程实现数模转换芯片DAC7311的输出电压的的设定,且利用INA132U差分运放及其后端电路构成的电压到电流的转换电路实现驱动电流的输出,电流输出范围可以从0～20mA不等。     

一种用于LCD源驱动芯片的数模转换电路设计

在LCD源驱动芯片设计中,为了将输入的数字信号转换成对应的灰阶电压,送到输出缓冲进行输出,需要一个数模转换电路.利用P.E.Allen在书中提到的电阻分压式D/A转换器结构,设计一种用于LCD源驱动芯片的6位数模转换电路.文中采用TSMC 0.25 μm CMOS工艺参数,用Cadence的spectre仿真器对电路进行仿真.电源电压为8 V,仿真的结果与理论上的数模转换电路传输特性基本吻合.     

一种高精度CMOS带隙基准电压源设计

介绍了带隙基准电压源的基本原理,设计了一种高精度带隙基准电压源电路.该电路采用中芯国际半导体制造公司0.18 μm CMOS工艺.Hspice仿真表明,基准输出电压在温度为-10～120 ℃时,温度系数为6.3×10-6/℃,在电源电压为3.0～3.6 V内,电源抑制比为69 dB.该电压基准在相变存储器芯片电路中,用于运放偏置和读出/写驱动电路中所需的高精度电流源电路.     

Nyquist电流型7位20MHz采样率CMOS数模转换器

介绍了一种高速7位DAC的设计及芯片测试结果,该DAC选取高5位单位电流源,低2位二进制电流源的分段结构。考虑了电流源匹配、毛刺降低以及版图中误差补偿等方面的问题来优化电路。流片采用0.35μmChartered双层多晶四层金属工艺,测试结果表明在20 MH z的采样频率下,微分非线性度和积分非线性度分别小于±0.2 LSB和±0.35 LSB。该DAC的满幅建立时间是20 ns,芯片面积为0.17 mm×0.23 mm。电源电压为3.3 V,功耗为3 mW。     

A 10-bit DAC with offset-adjustable op-amp for LCD column driver applications

This paper proposes a 10-bit digital-to-analog converter (DAC) consisting of a 6-bit resistive DAC (RDAC) and a 4-bit offset-adjustable op-amp for LCD column driver applications. The 6-bit RDAC selects only one voltage from the global resistor string before transmitting it to the op-amp. The op-amp implements 4-bit interpolation by adjusting the offset voltage. The maximal differential nonlinearity and integral nonlinearity of the proposed converter were measured at 0.8 LSB and 0.81 LSB, respectively, using 1LSB equal to 2 mV. The proposed 10-bit DAC occupies only 70 % of the space required for a conventional 8-bit RDAC.     

A low-Voltage 10-bit CMOS DAC in 0.01-mm/sup 2/ die area

A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18-/spl mu/m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. The DAC occupies 110 /spl mu/m/spl times/94 /spl mu/m die area. A segmented R-2R architecture is used for the DAC core in order to maximize matching accuracy for a minimal use of die area. A pseudocommon centroid layout is introduced to overcome the layout restrictions of conventional common centroid techniques. A linear current mirror is proposed in order to achieve linear output current with reduced voltage headroom. The measured differential nonlinearity by integral nonlinearity (DNL/INL) is better than 0.7/0.75 LSB and 0.8/2 LSB for 1.8-V and 1.4-V power supplies, respectively. The DAC remains monotonic (|DNL|<1 LSB) as INL reaches 4 LSB down to 1.3-V operation. The DAC consumes 2.2 mA of current at all supply voltage settings.     

A 10-bit 1.8 V 45 mW 100 MHz CMOS transmitter chip for use in an XDSL modem in a home network

This paper describes a 10-bit 1.8 V 45 mW 100 MHz transmitter chip (TX chip) that is fabricated using 0.18 μm 1P6 M CMOS technology for use in an xDSL modem in a home network. The chip is composed of a 10-bit segmented digital-to-analog converter (DAC) and a fully differential adaptive line driver (LD). In designing the DAC, the switched-current method is used to increase the conversion speed; the anti-process-variation current cell with threshold-voltage compensation is used to reduce the linearity error, and the current cell, with differential input and gain boosting, is used to minimize the feedthrough error and tapered error distribution. The circuit layout of the current source has four-phase symmetry, not only to increase the linearity but also to eliminate the gradient error. To design a fully differential adaptive LD, the feed-forward capacitor and quiescent current control circuit are used to reduce the zero-crossing distortion and to minimize the second-order harmonic. Additionally, the power efficiency is increased using an output-impedance matching circuit. Measurements reveal that, for a TX chip at a differential load of 100 Ω and a supplied voltage of 1.8 V, the efficient number of bits, operating frequency, output voltage, output current, power consumption, differential nonlinearity error and integral nonlinearity error are 9 bits, 100 MHz, ± 0.874 V, ± 10 mA, 45.8 mW, ?0.80 to +0.62 LSB, and ?0.92 to +0.82 LSB, respectively.     

LCoS伽马校正电路的研究

提出了一种应用于硅上液晶(LCoS)的伽马校正电路.双梯电阻数模转换器是伽马校正电路的一个重要组成部分.双梯电阻数模转换器由粗分电阻级和细分电阻级组成,其最大优点是占用版图面积小.提出的10位双梯电阻数模转换器仅由80个电阻、2个4-16译码器、1个2-4译码器和一些开关组成,供电电压是5 V.该数模转换器由0.35μm CMOS工艺实现.后仿真结果表明,数模转换器的微分非线性和积分非线性分别小于±0.5 LSB和±0.4 LSB.最后,对伽马校正电路进行了仿真,给出了伽马校正电路输出的液晶伽马校正曲线,仿真结果表明伽马校正电路能够满足LCoS显示系统的要求.

Abstract：

One gamma correction circuit for liquid crystal on silicon (LCoS) is proposed. Dual ladder resistor DAC (Digital to Analog Converter) is one of main components of the gamma correction circuit. Dual ladder resistor DAC consists of coarse resistor stage and fine resistor stage. The most advantage of the DAC is that its layout area is small. In this paper, the proposed 10-bit dual ladder resistor DAC only requires eighty resistors, two 4-to-16 decoders, one 2-to-4 decoder and some switches with a supply voltage of 5 V. This DAC is implemented by 0.35 m CMOS technology. The post simulation results that its differential non-linearity (DNL) and integral non-linearity (INL) are less than 0. 5 LSB and 0. 4 LSB, respectively. Meanwhile, the gamma correct circuit was simulated, and the gamma correction curve of liquid crystal is given. Simulation results show that the gamma correction circuit can meet the requirements of LCoS display system.     

集成LCoS芯片内的可编程多通道参考电压产生器

在LCoS显示芯片内集成参考电压产生器有很多优点,能产生更精确的参考电压、LCOS屏接口的外围引线更少、芯片系统的整体功耗更低、可靠性更高等.提出了集成LCOS芯片内的可编程多通道参考电压产生器的设计,分析了 LCoS 显示系统中参考电压的作用,给出了部分电路的原理图、版图以及电路低功耗的实现方法.整个电路系统有I2C接口电路、多通道寄存器、控制电路、多通道 DAC 以及多通道缓冲器组成.重点介绍了参考电压产生器中多通道 DAC 和多通道缓冲器的设计,并且用EDA设计工具完成了对部分电路原理图的设计和仿真.最后用SMIC CMOS工艺完成了电路版图的设计以及后续的ERC、DRC和LVS检测和验证.最后结果显示此电路系统能够完全满足 LCoS 显示的要求.     

LCoS芯片集成参考电压源的设计

提出了一种集成LCoS芯片内的可编程多通道参考电压源的设计,简单介绍了LCoS显示系统的工作原理,给出了参考电压源部分电路的原理图、版图以及电路低功耗的实现方法。参考电压源由I2C接口电路、多通道寄存器、控制电路、多通道DAC以及多通道缓冲器组成。重点介绍了参考电压源中多通道DAC和多通道缓冲器的设计,用EDA设计工具完成了对缓冲器原理图的设计和仿真。最后用SMICCMOS工艺完成了缓冲器版图的设计以及后续的ERC、DRC和LVS检查和验证,仿真结果显示此电路系统能够完全满足LCoS显示系统的要求。     

An untrimmed D/A converter with 14-bit resolution

Describes a monolithic 14-bit DAC which uses a new compensation technique for the DAC linearity, the `self-compensation technique', originated through a new concept. Since this technique automatically compensates for linearity error in the DAC by referring to a ramp function with about 17-bit linearity, a high precision DAC can be produced in monolithic form without the trimming of analog components. An experimental 14-bit DAC chip has been fabricated using analog compatible IIL technology and two-level metalization. A linearity error of less that /spl plusmn/1/2 LSB and a settling time of 1-2 /spl mu/s has been achieved.     

An 8-bit, 5 ns monolithic D/A converter subsystem

Describes a 5 ns settling time digital-to-analog converter device, which has been designed for use in video speed successive approximation analog to digital converters. The chip includes a precision reference source with a 25 ppm per degree C average temperature coefficient and a high-speed comparator. The successive approximation approach, restricted to low-speed converters until now, has the advantages of low cost and straightforward drive requirements. The achievement of the operating speeds described is dependent both on the circuit techniques used and the process employed. The DAC circuit, unlike most other devices, uses a multiple-matched current source array technique, which leads to a very linear, low glitch output. Without any form of trimming, most functional devices meet a /spl plusmn//SUP 1///SUB 2/ LSB differential and integral linearity specification, and many are /spl plusmn//SUP 1///SUB 4/ LSB or better.     

A 12-bit 1-Gword/s GaAs digital-to-analog converter system

The circuitry for a 12-b 1-Gword/s digital-to-analog converter (DAC) IC is described. A DC linearity of /spl plusmn/1/8 LSB has been preserved with this all-depletion GaAs MESFET chip. Dynamic measurements in the frequency domain indicate nonlinearities of less than -62 dBc at a 1-GHz clock rate. The DAC uses a very fast FET analog current switch that exhibits sufficiently low leakage currents for a 12-b linearity. The limited on-chip matching capabilities require the precision DC currents to be generated external to the GaAs chip. A current-switching DAC that partitions the high-speed functions onto a single GaAs chip while the high-precision bit currents are realized off-chip is described. The GaAs chip contains 12 1-b cells, each of which switches an analog bit current into a single sampler circuit that is shared by all the switches. The sampler is used to increase the dynamic linearity in the DAC.