Statistical methods for the estimation of process variation effects on circuit operation

In this paper, a technology computer-aided design (TCAD) driven method for accurate prediction of the performance spread of integrated circuits due to process variations is presented. The methodology starts with the development of the nominal process recipe and process simulators are calibrated to an existing process to obtain nominal device characteristics. After determining nominal process parameters, their variations are introduced followed by screening experiments to determine the relative effects of given process variations on the input-output delay and the average power dissipation in a circuit. Response surface models (RSMs) are then generated based on critical process factors identified. Process parameter optimization is performed using these RSM models to tune the mean circuit performance and to improve the yield. This methodology is demonstrated on a 33-stage ring oscillator manufactured with a CMOS design flow. The proposed methodology maps the process domain to design space, and plays a key role in design for manufacturability (DFM) to quantify direct impact of the process variations on circuits.     

Use of short-loop electrical measurements for yield improvement

Modern submicron processes are more sensitive to both random and systematic wafer-level process variation than ever before. Given the dimensional control limitations of new technologies, the amount of wafer-to-wafer and within wafer nonuniformity of many steps is becoming a significant fraction of the total error budget, which already includes the usual step-to-step allocations. However, a significant portion of the total observed variability is systematic in nature. Accordingly, particle defects may not continue to dominate parametric yield loss without improved understanding of parametric variations. In this paper, we demonstrate the use of short-loop electrical metrology to carefully characterize and decouple wafer-level variability of several critical processing steps. More specifically, we present our method and give results obtained from variability analyses for lithography critical dimension (CD) and inter-level dielectric (ILD) thickness control. Using statistically designed experiments and dedicated test structures, the main factors affecting dielectric thickness variability has been identified. The systematic variability from a wafer stepper has been extracted using a physically based statistical data filter. Once isolated, the deterministic variability can be modeled and controlled to enhance process and circuit design for manufacturability (DFM). We hope that in the future this work will be coupled with novel DFM-oriented CAD tools that encapsulate this information in a fashion that makes it useful to process and circuit designers     

Realistic statistical worst-case simulations of VLSI circuits

A simple and cost-effective method for evaluating the parametric product manufacturability of VLSI circuits is presented. The method, named gradient analysis, enables designers to predict the standard deviation of the circuit performance from measured or specified design parameter variations. This method, with a minimum extra design cost, avoids the overdesign associated with the traditional prediction of the worst-case performance of VLSI circuits. Gradient analysis also provides designers with information on the sensitivity of the circuit performance variations to the design parameter variations. In this way the key design parameters for process monitoring and control are identified. Experimental qualification of the method is discussed based on development and production data of VLSI products such as high-speed 1.2 μm 64 K CMOS static RAMs (SRAMs),     

Patterning tool characterization by causal variabilitydecomposition

A spatial and causal classification of process error provides opportunities for the accurate determination and efficient management of process error budget. Traditional metrology is posed with this dilemma: variability sampling requires cheap, highly repeatable metrology, such as electrical measurements, which also confound error sources of the variability sampled. In response, statistical metrology has been proposed as a novel combination of cost-effective metrology with subsequent statistical or experimental data processing to provide a technique that is capable of error decomposition into equipment causes. The methodology, consisting of 1) reticle and experiment design, 2) data filtering, and 3) error budget formulation, is presented and is general to a short-loop thin-film patterning sequence. A .35-μm polygate patterning sequence is chosen to demonstrate this technique. Reticle design and statistical filtering have been presented in a previous publication, and are summarized here. The second causal data filter is presented in this work, Aided by additional experimentation, a physical filter decomposes the separate contributions and interactions of the reticle and stepper. A portion of the error budget is calculated, including the effects of spatial correlation. The results of decomposition yields a numerical metric for equipment and process manufacturability. Results are presented that illustrate the use of the manufacturability metric in equipment selection and process design     

可制造性设计在纳米SOC中的应用和发展

随着图形特征尺寸的不断缩小、集成度的不断提高,集成电路已进入纳米系统芯片(SOC)阶段,摩尔定律依靠器件尺寸缩小得以延续的方式正面临着众多挑战。分析了纳米SOC中影响性能和良品率的关键效应及相应的措施。从半导体产业链的发展演变指出了可制造性设计(DFM)是纳米SOC阶段提高可制造性与良品率的解决方案。与光刻性能相关的分辨率增强技术(RET)是推动DFM发展的第一波浪潮,下一代的DFM将更注重良品率的受限分析及设计规则的综合优化。综述了DFM产生的历史及发展的现状,并对其前景进行了展望。     

Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits

The implementation of complex, high-performance digital functionality in nanometer CMOS technologies faces significant design and test challenges related to the increased susceptibility to process variations and environmental or operation-dependent disturbances. This paper proposes the application of unified semi-empirical propagation delay variation models to estimate the effect of Process, power supply Voltage, and Temperature (PVT) variations on the timing response of nanometer digital circuits. Experimental results based on electrical simulations of circuits designed in 65, 45, and 32?nm CMOS technologies are presented demonstrating that the models can be used for the analytical derivation of delay variability windows and delay variability statistical distributions associated to process variations. This information can be used during the design and test processes. On one hand, it allows the robustness of a given circuit in the presence of PVT variations to be assessed in the design environment. On the other hand, it allows boundaries between expected functional windows and those associated to abnormal behaviors due to delay faults to be defined. The main advantage of the proposed approach is that the effect of process variations on circuits’ performance can simultaneously be analyzed with those of power supply voltage and temperature variations. Experimental results have also been obtained on several FPGA boards including nanometer-scale Xilinx? and Altera? devices. These results provide a proof-of-concept, on real circuits, of the practical usefulness of the models.     

版图图形特征对铜电镀工艺的影响

铜电镀工艺后表面的不平整度通常取决于版图关键特征,包括线宽,线间距和金属密度。本文设计了一款测试芯片并在一家半导体厂加工制造。版图特征效应被真正的测试数据所检查和验证。通过分析金属蝶形、介质腐蚀、金属厚度和SEM照片,得出一些结论。线宽是决定表面形貌及产生铜金属蝶形和介质层腐蚀的最关键因素。经过铜电镀工艺发现,铜线越细铜生长的越厚,铜线越宽铜金属蝶形越大,发现了3种典型表面形貌。而且,通过测试数据,量化版图特征的影响并用曲率增强加速剂覆盖率的理论解释,这可以用于开发铜电镀工艺模型和开展可制造性设计研究。     

电气互联技术的现状及发展趋势

简要介绍了国外电气互联技术的现状，从电路可制造性设计、堆叠装配、FPC组装设计与工艺、PCB可制造性分析及虚拟设计技术、微波电路互联结构及绿色清洗技术等7个方面分析了电气互联先进制造技术的发展方向。     

基于DFM集成板级协同设计

基于DFM集成板级协同设计是在并行工程的指导下,将产品设计与产品制造、装配过程相集成的一种实用技术。介绍了DFM软件导入后的高阶应用,在产品开发中集成DFM协同设计包含板级设计与DFM分析协同,以及板级设计与MCAD之间的协同模式。通过具体案例,详细阐述了产品设计与工艺分析并行开展,提高产品设计质量和设计效率的操作方法。     

用在可制造性设计中的光刻规则检查

可制造性设计(DFM)已经发展成为优化通晓制造技术设计中的有效工具,它包含从理论、规则到工具的整体应用来提升从设计到硅片的流程.基于制程模型的光刻规则检查(LRC),可查出没被设计规则检查(DRC)出来的设计布局的不足之处.本设计把光刻规则检查加入到设计流程中,用来优化设计规则,改善布局更有利光学邻近效应修正,使布局图形有更大的制程窗口.     

High-throughput mapping of short-range spatial variations usingactive electrical metrology

Spatial variations of parameters in semiconductor manufacturing, such as critical dimension (CD) and overlay, have significant impact on the performance and yield of integrated circuits (IC). Among these spatial variations, the variations of parameters between transistors separated by a very short spatial distance such as 1 μm to 100 μm (intertransistor variations) can be particularly hazardous for those types of ICs that require exact transistor-transistor matching. To measure these intertransistor variations, both high-throughput and high-spatial-sampling-density beyond the scope of currently available metrology tools are needed. We have thus developed an active electrical metrology method of measuring intertransistor variations using on-chip, active, electrically addressable arrays of test structures to provide the high-throughput (5 μs/data point) and high-density (3 μm/grid spacing) needed. Test chips were designed and fabricated on a HP 0.35-μm process, and the testing configuration was set up to optimize throughput and precision. This method was verified with the measurements of on-chip calibration arrays. The spatial variations of both intertransistor CD (effective gate length) and overlay (between poly/diffusion) within the test chips were mapped with this method. For these circuits, the intertransistor CD variations were found to depend primarily on the layout, whereas the intertransistor overlay variations were found to be dominated by errors of the pattern generator used to fabricate the masks     

纳米集成电路 Cu CMP工艺模型参数优化

铜化学机械抛光受几何图形特性如线宽、间距和图形密度的影响,芯片和晶圆上铜互连线厚度的不均匀性都会影响电性能和降低良率。本文从物理化学的角度对CMP工艺进行了回顾和分析,针对Cu CMP制造工艺和在MIT提出的（Pattern-Density Step-Height,PDSH）模型基础上,建立与工艺相对应的三步骤工艺模型。为了扑捉工艺与版图结构的相关性,设计了一款65纳米测试芯片并在SMIC完成工艺实验。按照模型参数提取流程,通过芯片测试数据提取模型参数和验证工艺模型。模拟结果与测试结果对比说明二者趋势完全一致,最大偏差小于5 nm。第三方测试数据进一步证明模型参数优化取得很好的结果。精准的Cu CMP工艺模型可以用于做芯片的DFM检查、显示和消除关键热点,从而确保芯片的良率和集成电路量产能力。     

Statistical computer-aided design for microwave circuits

A useful methodology for microwave circuit design is presented. A statistical technique known as Design of Experiments is used in conjunction with computer-aided design (CAD) tools to obtain simple mathematical expressions for circuit responses. The response models can then be used to quantify response trade-offs, optimize designs, and minimize circuit variations. The use of this methodology puts the designer's intelligence back into design optimization while making “designing for circuit manufacturability” a more systematic and straightforward process. The method improves the design process, circuit performance, and manufacturability. Two design examples are presented in context to the new design methodology     

超深亚微米与纳米级标准单元的可制造性设计与验证技术

当半导体工业进入到超深亚微米时代后,标准单元的设计面临着新的挑战.由于亚波长光刻的使用,图形转移质量将严重下降.在这种情况下,以集成电路的可制造性作为目标的"可制造性设计"方法在标准单元设计中变得至关重要.本文分析了超深亚微米与纳米工艺条件下标准单元设计中遇到的一些典型可制造性问题,提出了相应的新设计规则和解决方案,完成了实际90nm工艺下标准单元的可制造性设计工作.同时,文中提出了包括光刻模拟、测试电路组等技术在内的单元可制造性设计和验证的流程.     

统计学在数字电路后端时序分析中的应用

随着半导体工艺技术的不断进步,芯片制造中的工艺变量,越来越难以控制。于是,数字电路后端设计对时序分析提出了更多的要求。越来越多的进程、电源电压、温度（PVT）等工艺角（corner）传统的静态时序分析方法（STA）变得越来越难以精确地估计制程变异（variation）对于设计性能的影响。在本文中,将会介绍一种新的基于统计学的时序分析方法：Statistical Static Timing Analysis （SSTA）。通过一组附加的数据：精确的制程变异描述文件、统计学标准的库文件,SSTA有望在未来取代传统的静态时序分析方法,从而更好的驾驭越来越先进的半导体工艺技术,以及千万门级高速芯片的设计要求。     

Sensitivity of double-gate and FinFETDevices to process variations

We investigate the manufacturability of 20-nm double-gate and FinFET devices in integrated circuits by projecting process tolerances. Two important factors affecting the sensitivity of device electrical parameters to physical variations were quantitatively considered. The quantum effect was computed using the density gradient method and the sensitivity of threshold voltage to random dopant fluctuation was studied by Monte Carlo simulation. Our results show the 3/spl sigma/ value of V/sub T/ variation caused by discrete impurity fluctuation can be greater than 100%. Thus, engineering the work function of gate materials and maintaining a nearly intrinsic channel is more desirable. Based on a design with an intrinsic channel and ideal gate work function, we analyzed the sensitivity of device electrical parameters to several important physical fluctuations such as the variations in gate length, body thickness, and gate dielectric thickness. We found that quantum effects have great impact on the performance of devices. As a result, the device electrical behavior is sensitive to small variations of body thickness. The effect dominates over the effects produced by other physical fluctuations. To achieve a relative variation of electrical parameters comparable to present practice in industry, we face a challenge of fin width control (less than /spl sim/1 nm 3/spl sigma/ value of variation) for the 20-nm FinFET devices. The constraint of the gate length variation is about 10/spl sim/15%. We estimate a tolerance of 1/spl sim/2 /spl Aring/ 3/spl sigma/ value of oxide thickness variation and up to 30% front-back oxide thickness mismatch.     

Analysis of mixed-signal manufacturability with statisticaltechnology CAD (TCAD)

We have developed a methodology which combines technology CAD (TCAD) simulation with statistical analysis of empirical data to predict and control the manufacturability of IC fabrication processes. As a result, manufacturing tolerance or sigma-based models (also known as worst-case models) can be determined before a significant sample size of fabricated devices can be characterized. Early on in the development cycle, empirical data is collected, and models built from simulated data are refined. These revised models are used to determine process control limits, and optimize in-line and electrical test measurement (E-test) for maximum observability of variation. As the process is stabilized, further refined models are used to perform yield diagnosis and tolerance analysis of circuits. This methodology has been applied to a number of BJT and submicrometer CMOS processes to create predictive sigma-based models, modify the fabrication recipe to meet objective specifications as development proceeds, and finally use them to control the manufacturing line     

Regular FPGA based on regular fabric

In the sub-wavelength regime,design for manufacturability(DFM) becomes increasingly important for field programmable gate arrays(FPGAs).In this paper,an automated tile generation flow targeting micro-regular fabric is reported.Using a publicly accessible,well-documented academic FPGA as a case study,we found that compared to the tile generators previously reported,our generated micro-regular tile incurs less than 10%area overhead,which could be potentially recovered by process window optimization,thanks to its superior printability. In addition,we demonstrate that on 45 nm technology,the generated FPGA tile reduces lithography induced process variation by 33%,and reduce probability of failure by 21.2%.If a further overhead of 10%area can be recovered by enhanced resolution,we can achieve the variation reduction of 93.8%and reduce the probability of failure by 16.2%.     

A 1.5-GHz 130-nm Itanium/sup /spl reg// 2 Processor with 6-MB on-die L3 cache

This 130-nm Itanium 2 processor implements the explicitly parallel instruction computing (EPIC) architecture and features an on-die 6-MB 24-way set-associative level-3 cache. The 374-mm/sup 2/ die contains 410 M transistors and is implemented in a dual-V/sub t/ process with six Cu interconnect layers and FSG dielectric. The processor runs at 1.5 GHz at 1.3 V and dissipates a maximum of 130 W. This paper reviews circuit design and package details, power delivery, the reliability, availability, and serviceability (RAS) features, design for test (DFT), and design for manufacturability (DFM) features, as well as an overview of the design and verification methodology. The fuse-based clock deskew circuit achieves 24-ps skew across the entire die, while the scan-based skew control further reduces it to 7 ps. The 128-bit front-side bus has a bandwidth of 6.4 GB/s and supports up to four processors on a single bus.