Minimization of switching activities of partial products for designing low-power multipliers

This work presents low-power 2's complement multipliers by minimizing the switching activities of partial products using the radix-4 Booth algorithm. Before computation for two input data, the one with a smaller effective dynamic range is processed to generate Booth codes, thereby increasing the probability that the partial products become zero. By employing the dynamic-range determination unit to control input data paths, the multiplier with a column-based adder tree of compressors or counters is designed. To further reduce power consumption, the two multipliers based on row-based and hybrid-based adder trees are realized with operations on effective dynamic ranges of input data. Functional blocks of these two multipliers can preserve their previous input states for noneffective dynamic data ranges and thus, reduce the number of their switching operations. To illustrate the proposed multipliers exhibiting low-power dissipation, the theoretical analyzes of switching activities of partial products are derived. The proposed 16 /spl times/ 16-bit multiplier with the column-based adder tree conserves more than 31.2%, 19.1%, and 33.0% of power consumed by the conventional multiplier, in applications of the ADPCM audio, G.723.1 speech, and wavelet-based image coders, respectively. Furthermore, the proposed multipliers with row-based, hybrid-based adder trees reduce power consumption by over 35.3%, 25.3% and 39.6%, and 33.4%, 24.9% and 36.9%, respectively. When considering product factors of hardware areas, critical delays and power consumption, the proposed multipliers can outperform the conventional multipliers. Consequently, the multipliers proposed herein can be broadly used in various media processing to yield low-power consumption at limited hardware cost or little slowing of speed.     

Designing of low-power data oriented adders

The paper presents an idea of designing of low-power adders addressed to specific data processing. Mainly, the idea consists in proper choosing of 1-bit full adder cells for given probability of summed data, to obtain reduction in consumed power. Additionally different structures of the cells can be used, in one design, if it leads to reduction of power dissipation. To proper choice of structures of 1-bit full adders theirs energy characteristic versus summed data is needed. So, at the beginning we present results of assessment of a few 1-bit adder cells selected from literature and designed in UMC180 CMOS technology. The extended model of power consumption, taking into consideration input vector changes, was used, giving more accurate values than traditional model based on switching activity only. Thanks to the use of this model, obtained results allow detailed analysis of 1-bit adders on account of the using them in designing of low-power multi-bit adders summing specific data. Based on the results of analyses and given characteristic of summed data, appropriate full adder cells can be chosen to the final design of low-power data oriented adder. In specific case, cells which are made in different techniques can be used in multi-bit adder. A few examples are shown at the end of the paper.     

基于多数决定逻辑非门的低功耗全加器设计

全加器是算术运算的基本单元,提高一位全加器的性能是提高运算器性能的重要途径之一。首先提出多数决定逻辑非门的概念和电路设计,然后提出一种基于多数决定逻辑非门的全加器电路设计。该全加器仅由输入电容和CMOS反向器组成,较少的管子、工作于极低电源电压、短路电流的消除是该全加器的三个主要特征。对这种新的全加器,用PSpice进行了晶体管级模拟。结果显示,这种新的全加器能正确完成加法器的逻辑功能。     

A high-accuracy approximate adder with correct sign calculation

Conventional precise adders take long delay and large power consumption to obtain accurate results. Exploiting the error tolerance of some applications such as multimedia, image processing, and machine learning, a number of recent works proposed to design approximate adders that generate inaccurate results occasionally in exchange for reduction in delay and power consumption. However, most of the existing approximate adders have a large relative error. Besides, when applied to 2's complement signed addition, they sometimes generate a wrong sign bit. In this paper, we propose a novel approximate adder that exploits the generate signals for carry speculation. Furthermore, we introduce a low-overhead module to reduce the relative error and a sign correction module to fix the sign error. Compared to the conventional ripple carry adder and carry-lookahead adder, our adder with block size of 4 reduces power-delay product by 66% and 32%, respectively, for a 32-bit addition. Compared to the existing approximate adders, our adder significantly reduces the maximal relative error and ensures correct sign calculation with comparable area, delay, and power consumption. We further tested the performance of our adders with and without the sign error correction module in three real applications, mean filter, edge detection, and k-means clustering. The experimental results demonstrated the importance of reducing the relative error and ensuring the correct sign calculation for 2's complement signed additions. The outputs produced using our adder with the sign error correction module are very close to those produced using accurate adder.     

基于流水线的自检测进位相关和加法器设计

文章提出了一种基于流水线设计的具有自检测功能的进位相关和加法器。该加法器包括四个8位进位相关和加法器（CDSA）．一个4位超前进位单元（BLCU）和一个奇偶校验器。与普通的行波进位加法器相比，文章设计的加法器硬件实现面积仅增加3．85％，而在关键路径的延时上，该加法器要减少39．2％。     

A novel multiplexer-based low-power full adder

The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF and 10T ) and is 64% faster.     

Constant addition with flagged binary adder architectures

The goal of this paper is to present architectures that provide the flexibility within a regular adder to augment/decrement the sum of two numbers by a constant. This flexibility adds to the functionality of a regular adder, achieving a comparable performance to conventional designs, thereby eliminating the need of having a dedicated adder unit to perform similar tasks. This paper presents an adder design to accomplish three-input addition if the third operand is a constant. This is accomplished by the introduction of flag bits. Such designs are called Enhanced Flagged Binary Adders (EFBA). It also examines the effect on the performance of the adder when the operand size is expanded from 16 bits to 32 and 64 bits. A detailed analysis has been provided to compare the performance of the new designs with carry-save adders in terms of delay, area and power.     

A novel low-power full-adder cell for low voltage

This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the time-consuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-μm CMOS process technology. The adder cell is compared with seven widely used adders based on power consumption, speed, power-delay product (PDP) and area efficiency. Intensive simulation runs on a Cadence environment and HSPICE show that the new adder has more than 11% in power savings over a conventional 28-transistor CMOS adder. In addition, it consumes 30% less power than transmission function adder (TFA) and is 1.11 times faster.     

Minimal Energy Asynchronous Dynamic Adders

In battery-operated portable or implantable digital devices, where battery life needs to be maximized, it is necessary to minimize not only power consumption but also energy dissipation. Typical energy optimization measures include voltage reduction and operating at the slowest possible speed. We employ additional methods, including hybrid asynchronous dynamic design to enable operating over a wide range of battery voltage, aggregating large combinational logic blocks, and transistor sizing and reordering. We demonstrate the methods on simple adders, and discuss extension to other circuits. Three novel adders are proposed and analyzed: a 2-bit pass transistor logic (PTL) adder and two dynamic 2-bit adders. Circuit simulations on a 0.18-mum process at low voltage show that leakage energy is below 1%. The proposed adders achieve up to 40% energy savings relative to previously published results, while also operating faster     

Evaluation of three 32-bit CMOS adders in DCVS logic for self-timedcircuits

The efficient implementation of adders in differential logic can be carried out using a new generate signal (N) presented in this paper. This signal enables iterative shared transistor structures to be built with a better speed/area performance than a conventional implementation. It also allows adders developed in domino logic to be easily adapted to differential logic. Based on this signal, three 32-b adders in differential cascode switch voltage (DCVS) logic with completion circuit for applications in self-timed circuits have been fabricated in a standard 1.0-μm two-level metal CMOS technology. The adders are: a ripple-carry (RC) adder, a carry look-ahead (CLA) adder, and a binary carry look-ahead (BCL) adder. The RC adder has the best levels of performance for random input data, but its delay is significantly influenced by the length of the carry propagation path, and thus is not recommended in circuits with nonrandom input operands. The BCL adder is the fastest but has a high cost in chip area. The CLA adder provides an intermediate option, with an area which is 20% greater than that of the RC adder. Its average delay is slightly greater than that of the other two adders, with an addition time which increases slowly with the carry propagate length even for adders with a high number of bits     

A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic

A high speed and low power 8-bit carry-lookahead adder using two-phase modified dual-threshold voltage (dual-V_t) domino logic blocks which are arranged in a programmable logical array-like design style with pipelining is presented. The modified domino logic circuits employ dual-transistors and reversed bulk-source biases for reducing subthreshold leakage current when advanced deep submicrometer process is used. Moreover, an nMOS transistor is inserted in the discharging path of the output inverter such that the modified domino logic can be properly applied in a pipeline structure to reduce the power consumption. The addition of two 8-bit binary operands is executed in two cycles. Not only is it proven to be also suitable for long adders, the dynamic power consumption is also drastically reduced by more than 10% by the measurement results on silicon.     

Systematic synthesis of approximate adders and multipliers with accurate error calculations

In this study, we perform logic synthesis and area optimization of approximate ripple-carry adders and Wallace-tree multipliers with a given error constraint. We first implement approximate 1-bit adders having different error rates as building blocks of the proposed multi-bit adders and multipliers. In implementations, we exploit offsetting errors in carry and sum outputs of the adders. Also we take into account the probability of occurrence of input assignments. Using the implemented 1-bit adders, we systematically synthesize multi-bit adders and multipliers proceeding from the least to the most significant bits. We design the ripple-carry adders such that their successive 1-bit approximate adders cannot produce build-up errors. We design the Wallace-tree multipliers by considering the fact that their building blocks of 1-bit adders might have different probabilities of occurrence for different input assignments. As a result, the proposed adders and multipliers, implemented using the Cadence Genus tool with TSMC 0.18μ m CMOS technology, offer in average a 25% smaller circuit area, and correspondingly power consumption, compared to the circuits proposed in the literature by satisfying the same error constraint. We also evaluate the adders and multipliers in image processing applications as well as within artificial neural networks.     

High Speed Error Tolerant Adder for Multimedia Applications

In this paper, a 1-bit modified full adder (MFA) cell is proposed. This eliminates the carry propagation during the addition by allowing errors in the carry bit. Using the proposed MFA, a 16-bit high speed error tolerant adder (HSETA) circuit is designed with conventional carry select adder (CSLA) structure for higher order bits and MFA based structure for lower order bits. The performance of HSETA is compared with existing adders in terms of accuracy, gate count, delay and power dissipation. The gate count of the HSETA is reduced by 23% and speed is improved by 43% compared to a conventional 16-bit adder structure. Further, implementation on FPGA Spartan 6 shows that HSETA uses 53% fewer LUT and 63% fewer slices compared to the conventional adder. Image blending application is used to evaluate the performance of the HSETA. In addition, to perform extensive error analysis, an analytical model is developed for HSETA and tested for varying bit widths and input probabilities. The analytical model is validated through simulation.     

Partitioning and gating technique for low-power multiplication in video processing applications

In this paper, we propose a partitioning and gating technique for the design of a high performance and low-power multiplier for kernel-based operations such as 2D convolution in video processing applications. The proposed technique reduces dynamic power consumption by analyzing the bit patterns in the input data to reduce switching activities. Special values of the pixels in the video streams such as zero, repeated values or repeated bit combinations are detected and data paths in the architecture design are disabled appropriately to eliminate unnecessary switching. Input pixels in the video stream are partitioned into halves to increase the possibility of detecting special values. It is observed that the proposed scheme helps to reduce dynamic power consumption in the 2D convolution operations up to 33%.     

Design for Low Power Testing of Computation Modules with Contiguous Subspace in VLSI

A kind of pseudo Gray code presentation of test patterns based on accumulation generators is presented and a low power test scheme is proposed to test computational function modules with contiguous subspace in very large scale integration （VLSI）, especially in digital signal processors （DSP）. If test patterns from accumulators for the modules are encoded in the pseudo Gray code presentation, the switching activities of the modules are reduced, and the decrease of the test power consumption is resulted in. Results of experimentation based on FPGA show that the test approach can reduce dynamic power consumption by an average of 17.40% for 8-bit ripple carry adder consisting of 3-2 counters. Then implementation of the low power test in hardware is exploited. Because of the reuse of adders, introduction of additional XOR logic gates is avoided successfully. The design minimizes additional hardware overhead for test and needs no adjustment of circuit structure. The low power test can detect any combinational stuck-at fault within the basic building block without any degradation of original circuit performance.     

Low power multipliers based on new hybrid full adders

Five hybrid full adder designs are proposed for low power parallel multipliers. The new adders allow NAND gates to generate most of the multiplier partial product bits instead of AND gates, thereby lowering the power consumption and the total number of needed transistors. For an 8×8 implementation, the ALL-NAND array multiplier achieves 15.7% and 7.8% reduction in power consumption and transistor count at the cost of a 6.9% increase in time delay compared to standard array multiplier. The ALL-NAND tree multiplier exhibits lower power consumption and transistor count by 12.5% and 7.3%, respectively, with a 4.4% longer time delay, compared to conventional tree multiplier.     

Power-Aware Design of An 8-Bit Pipelining ANT-Based CLA Using Data Transition Detection

A high speed and low-power 8-bit carry-lookahead adder (CLA) using two-phase all-N-transistor (ANT) blocks which are arranged in a PLA design style with power-aware pipelining is presented. The pull-up charging and pull-down discharging of the transistor arrays of the PLA are accelerated by inserting two feedback MOS transistors between the evaluation NMOS blocks and the outputs. The analysis of the area (transistor count) tradeoff is also provided in this work. The output of the addition of two 8-bit binary numbers is done in two cycles. The proposed power-aware pipelining design methodology using a simple data transition detection circuit takes advantage of shutting down the processing stages with identical inputs in two consecutive cycles. The data transition detection circuit is used to monitor the state switching of input data. Not only is it proved to be also suitable for long adders, the power consumption is drastically reduced by at most 50% at every process corner.

Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding

Carry-select adders are one of the faster types of adders. This paper proposes a scheme that encodes the sum bits using two-rail codes; the encoded sum bits are then checked by self-checking checkers. The multiplexers used in the adder are also totally self-checking. The scheme is illustrated with the implementation of a 2-bit carry select adder that can detect all single stuck-at faults on-line; the detection of double faults is not guaranteed. Adders of arbitrary size can be constructed by cascading the appropriate number of such 2-bit adders. A range of adders from 4 to 128 bits is designed using this approach employing a 0.5-mum CMOS technology. The transistor overhead in implementing these self-checking adders varies from 19.51% to 20.94%, and the area overhead varies from 16.07% to 20.67% compared to adders without built-in self-checking capability.     

A novel approach to high-level switching activity modeling withapplications to low-power DSP system synthesis

We address high-level synthesis of low-power digital signal processing (DSP) systems by using efficient switching activity models. We present a technology-independent hierarchical scheme that can be easily integrated into current communications/DSP CAD tools for comparing the relative power/performance of two competing DSP designs without specific knowledge of transistor-level details. The basic building blocks considered for such systems are a full adder, a half adder, and a one-bit delay. Estimates of the switching activity at the output of these primitives are used to model the activity in more complex building blocks of DSP systems. The presented hierarchical method is very fast and simple. The accuracy of estimates obtained using the proposed approach is shown to be within 4% of the results obtained using extensive bit-level simulations. Our approach shows that the choice of multiplier/multiplicand is important when using array multipliers in a datapath. If the input signal with smaller mean square value is chosen as the multiplicand, almost 20% savings in switching activity can be achieved. This observation is verified by an analog simulation using a 16 × 16 bit array multiplier implemented in a 0.6-μ process with 3.3 V supply voltage     

Efficient Addition Circuits for Modular Design of Processors-in-Memory

This paper presents the design of a new dynamic modular addition circuit optimized for the integration into high-speed low-power processors-in-memory (PIMs). The proposed architecture is based on a hybrid ripple-carry/carry-look ahead/carry-bypass approach. In order to reach the required computational speed and the limited power dissipation, the circuit described here is divided into two independent submodules interfaced through dynamic latches. Furthermore, the proposed adder operates in the single instruction multiple data fashion, therefore it is able to manage different operand wordlengths. Our PIM architecture is based on slices containing 16-bit adders. Therefore, the main specification of the design described here is to minimize the effect on speed performance caused by cascading 16-bit blocks. Using a bulk CMOS UMC 0.18-$muhbox m$1.8-V process, the optimized version of the 64-bit circuit here proposed, obtained realizing a rippling chain of four 16-bit blocks, shows a power-delay product of only 38.8$hbox pJ^asthbox ns$and requires less than 4300 transistors.