DSOI总剂量效应模型及背偏调控模型

总剂量辐射效应会导致绝缘体上硅金属氧化物半导体场效应晶体管(DSOI MOSFET)器件的阈值电压漂移、泄漏电流增大等退化特性。由于背栅端口的存在,SOI器件存在新的总剂量效应加固途径,对于全耗尽SOI器件,利用正背栅耦合效应,可通过施加背栅偏置电压补偿辐照导致的器件参数退化。本文研究了总剂量辐照对双埋氧层绝缘体上硅金属氧化物半导体场效应晶体管(DSOI MOSFET)总剂量损伤规律及背栅偏置调控规律,分析了辐射导致晶体管电参数退化机理,建立了DSOI晶体管总剂量效应模拟电路仿真器(SPICE)模型。模型仿真晶体管阈值电压与实测结果≤6 mV,同时根据总剂量效应模型给出了相应的背栅偏置补偿模型,通过晶体管背偏调控总剂量效应SPICE模型仿真输出的补偿电压与试验测试结果对比,N型金属氧化物半导体场效应晶体管(NMOSFET)的背偏调控模型误差为9.65%,P型金属氧化物半导体场效应晶体管(PMOSFET)为5.24%,该模型可以准确反映DSOI器件辐照前后阈值特性变化,为器件的背栅加固提供参考依据。     

SOI NMOS侧壁晶体管总剂量辐射效应电流模型

针对绝缘体上硅(SOI)NMOS侧壁晶体管的电流特性研究,利用Verilog-A语言建立了一个含有漏致势垒降低(DIBL)效应的侧壁晶体管电流模型。进一步基于SOI NMOS总剂量辐射效应机理将总剂量辐射效应引入该模型。新建立的侧壁晶体管电流模型既保留了侧壁晶体管本身的电流特性,又可以反映总剂量辐射导致的电流变化。将新的侧壁晶体管总剂量模型嵌入商用SOI模型仿真验证的结果表明,该SOI侧壁晶体管总剂量模型在不同漏端偏置电压下的仿真与测试结果高度吻合,可以给电路设计者提供可靠的仿真结果,缩短抗辐射电路开发周期。     

栅长对深亚微米器件总剂量辐射诱生漏电流的影响研究

对0.18 um 工艺NMOSFET器件进行总剂量辐照实验,包括不同栅长器件。由于深亚微米器件栅氧化层厚度较薄,对总剂量辐照不敏感,辐照前后器件阈值电压基本不发生变化。所有尺寸器件的关态漏电流随总剂量增加而增加。我们认为,总剂量辐射在浅沟槽隔离氧化物侧壁诱生成源漏之间漏电路径。该漏电路径是由于浅沟槽隔离氧化物种陷阱正电荷形成的。研究发现,辐射诱生的漏电流大小与器件栅长密切相关。通过主晶体管和寄生晶体管模型可以很好解释该现象。     

沟道热载流子导致的SOI NMOSFET's的退化特性

研究了沟道热载流子效应引起的SOI NMOSFET's的退化.在中栅压应力(Vg≈Vd/2)条件下,器件退化表现出单一的幂律规律;而在低栅压应力(Vgs≈Vth)下,由于寄生双极晶体管(PBT)效应的影响,多特性的退化规律便会表现出来,漏电压的升高、应力时间的延续都会导致器件退化特性的改变.对不同应力条件下的退化特性进行了详细的理论分析,对SOI NMOSFET'S器件退化机理提出了新见解.     

沟道热载流子导致的SOI NMOSFET's的退化特性

研究了沟道热载流子效应引起的SOI NMOSFET's的退化.在中栅压应力(Vg≈Vd/2)条件下,器件退化表现出单一的幂律规律;而在低栅压应力(Vgs≈Vth)下,由于寄生双极晶体管(PBT)效应的影响,多特性的退化规律便会表现出来,漏电压的升高、应力时间的延续都会导致器件退化特性的改变.对不同应力条件下的退化特性进行了详细的理论分析,对SOI NMOSFET'S器件退化机理提出了新见解.     

总剂量辐射对0.5μm部分耗尽SOI CMOS器件的影响

介绍了基于SIMOX SOI晶圆的0.5μm PD SOI CMOS器件的抗总剂量辐射性能。通过CMOS晶体管的阈值电压漂移,泄漏电流和32位DSP电路静态电流随总剂量辐射从0增加到500 krad(Si)的变化来表现该工艺技术的抗电离总剂量辐射能力。对于H型(无场区边缘)NMOS晶体管,前栅阈值电压漂移小于0.1 V;对于H型PMOS晶体管,前栅阈值电压漂移小于0.15 V;未发现由辐射引起的显著漏电。32位DSP电路在500 krad(Si)范围内,静态电流小于1 m A。通过实验数据表明,在较高剂量辐射条件下,利用该工艺制造的ASIC电路拥有良好的抗总剂量辐射性能。     

漏及衬底偏压对深亚微米工艺器件总剂量效应的影响

本文对采用0.18?m工艺制造的NMOS器件辐射总剂量效应进行了研究。对晶体管进行了不同剂量的₆₀Co辐射实验,同时测试了辐照前后晶体管电学参数随漏、衬底偏压的变化的规律。采用STI寄生晶体管模型来解释晶体管的关态漏电流及阈值电压漂移性质。3D器件仿真验证了模型的准确性。     

边缘注入对H型栅SOI pMOSFETs亚阈值泄漏电流的影响

就不同边缘注入剂量对H型栅SOI pMOSFETs亚阈值泄漏电流的影响进行了研究。实验结果表明不足的边缘注入将会产生边缘背栅寄生晶体管，并且在高的背栅压下会产生明显的泄漏电流。分析表明尽管H型栅结构的器件在源和漏之间没有直接的边缘泄漏通路，但是在有源扩展区部分，由于LOCOS技术引起的硅膜减薄和剂量损失仍就促使了边缘背栅阈值电压的降低。     

提高SOI器件和电路性能的研究

在分析SOI器件的浮体效应、击穿特性、背栅阈值、边缘漏电、ESD及抗辐照特性的基础上,提出了提高SOI器件和电路性能的技术途径.体接触是防止浮体效应的最好方法;正沟道和背沟道的BF2/B离子注入可以分别满足阈值和防止背栅开启的需要;SOI器件栅电极的选取严重影响器件的性能;源区的浅结有助于减小寄生npn双极晶体管的电流增益;而自对准硅化物技术为SOI器件优良特性的展现发挥了重要作用.研究发现,采用综合加固技术的nMOS器件,抗总剂量的水平可达1×106rad(Si).     

抗辐射高压SOI NMOS器件的背栅效应研究

通过对高压SOI NMOS器件进行总剂量辐照试验发现,辐照后器件埋氧化层中引入了大量的氧化层陷阱电荷,使得器件背栅发生反型,在较高漏极工作电压下,漏极耗尽区与反型界面相连,使得源漏发生穿通,导致器件漏电。通过原理分析提出了增加顶层硅膜厚度的优化措施,证明在顶层硅膜较薄的情况下,SOI NMOS器件容易发生总剂量辐照后背栅漏电,厚顶层硅器件特性受背栅辐照效应的影响则显著降低直至消失。     

基于TCAD的绝缘体上硅器件总剂量效应仿真技术研究

绝缘体上硅（Silicon-on-Insulator,SOI）器件的全介质隔离结构改善了其抗单粒子效应性能,但也使其对总剂量效应更加敏感.为了评估SOI器件的总剂量效应敏感性,本文提出了一种基于TCAD （Technology Computer Aided Design）的总剂量效应仿真技术.通过对SOI器件三维结构进行建模,利用TCAD内置的辐射模型开展瞬态仿真,模拟氧化层中辐射感应电荷的产生、输运和俘获过程,从而分别评估绝缘埋层（Buried Oxide,BOX）和浅沟槽隔离（Shallow Trench Isolation,STI）氧化层中辐射感应陷阱电荷对器件电学性能的影响.基于该仿真技术,本文分别研究了不同偏置、沟道长度、体区掺杂浓度以及STI形貌对SOI MOSFET器件总剂量辐射效应的影响.仿真结果表明高浓度的体区掺杂、较小的STI凹槽深度和更陡峭的STI侧壁将有助于改善SOI器件的抗总剂量效应性能.     

总剂量辐照对65 nm NMOSFET热载流子敏感参数的影响

为了研究总剂量辐射对纳米MOS晶体管热载流子效应的影响,对65 nm 体硅工艺的NMOS器件进行了总剂量辐射和热载流子试验,对比了辐射前后不同宽长比器件的跨导、栅极泄漏电流、线性饱和电流等电参数。结果表明,MOS器件的沟道宽度越窄,热载流子效应受辐射的影响越显著,总剂量辐射后热载流子效应对器件的损伤增强。分析认为,辐射在STI中引入的陷阱电荷是导致以上现象的主要原因。该研究结果为辐射环境下器件的可靠性评估提供了依据。     

一种抗总剂量辐照的新型PD SOI器件

提出了一种具有叠层埋氧层的新栅型绝缘体上硅(SOI)器件。针对SOI器件的抗总电离剂量(TID)加固方案,对绝缘埋氧层(BOX)采用了叠层埋氧方案,对浅沟槽隔离(STI)层采用了特殊S栅方案。利用Sentaurus TCAD软件,采用Insulator Fixed Charge模型设置固定电荷密度,基于0.18μm CMOS工艺对部分耗尽(PD)SOI NMOS进行了TID效应仿真,建立了条栅、H栅、S栅三种PD SOI NMOS器件的仿真模型。对比三种器件辐照前后的转移特性曲线、阈值电压漂移量、跨导退化量,验证了该器件的抗TID辐照性能。仿真结果表明,有S栅的器件可以抗kink效应,该PD SOI NMOS器件的抗TID辐照剂量能力可达5 kGy。     

Total ionizing dose effect in 0.2 μm PDSOI NMOSFETs with shallow trench isolation

This paper presents the total ionizing dose radiation performance of 0.2 μm PDSOI NMOS devices under different bias conditions. The hump effect is observed in the transfer characteristic of the back gate device instead of the front gate device after radiation. A STI bottom corner parasitic transistor model is proposed to explain this phenomenon. It also provides a simple way to extract the effective sheet charge density along the STI sidewall. Three-dimensional simulation was applied to explain the radiation effect. It shows that charge trapped in the shallow trench isolation, particularly at the bottom region of the trench oxide where the STI and the BOX are connected, is the dominant contributor to the off-state drain-to-source leakage current. The dimension of the transistor plays an important role on influencing the device’s performance after radiation. Larger off-state leakage current and radiation induced threshold voltage shift are reported in the narrow channel device than in the wide channel one. Different TID responses due to the STI process variation are also discussed.     

Influences of silicon-rich shallow trench isolation on total ionizing dose hardening and gate oxide integrity in a 130 nm partially depleted SOI CMOS technology

The influences of silicon-rich shallow trench isolation (STI) on total ionizing dose (TID) hardening and gate oxide integrity (GOI) in a 130 nm partially depleted silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology are investigated. Radiation-induced charges buildup in STI oxide can invert the parasitic sidewall channel of the n-channel transistor, which will increase the off-state leakage current and decrease the threshold voltage for the main transistor. Compared with the general STI process, the silicon-rich STI process can significantly suppress the increase in leakage current and negative shifts in subthreshold region induced by the total dose radiation, implying TID hardening for STI trench oxide. However, the silicon-rich STI process has a deleterious impact on GOI. It leads to the thin gate oxide thickness at trench corner and lowers the gate oxide breakdown voltage. Issues of gate oxide integrity induced by silicon-rich STI are investigated in this paper, and an optimized process to solve this problem is proposed and examined. Finally, the TID response of the optimized silicon-rich STI process is presented in comparison to the general and silicon-rich STI processes.     

An anomalous device degradation of SOI narrow width devices causedby STI edge influence

The effects of shallow trench isolation (STI) on silicon-on-insulator (SOI) devices are investigated for various device sizes with three different gate shapes. Both NMOSFETs and PMOSFETs with the channel region butted to the STI show a reduction in mobility (NMOSFETs and PMOSFETs) and an increase of low-frequency noise as the channel width is reduced. In comparison, the devices without the STI-butted channel region show much less variation in mobility for various channel widths. The degradation of MOSFET yield in SOI MOSFETs with the STI is found to be dependent on the device width since the contribution of the interface roughness (or damage) between the STI and the channel formed during the dry etch process becomes significant with the decrease of channel width and the increase of channel length. From the charge-pumping results, the interface state (N_it) generated by the STI process was identified as the cause of the anomalous degradation     

A temperature-dependent SOI MOSFET model for high-temperatureapplication (27 °C-300 °C)

A temperature-dependent model for long-channel silicon-on-insulator (SOI) MOSFETs for use in the temperature range 27 °C-300 °C, suitable for circuit simulators such as SPICE, is presented. The model physically accounts for the temperature-dependent effects in SOI MOSFETs (such as threshold-voltage reduction, increase of leakage current, decrease of generation due to impact ionization, and channel mobility degradation with increase of temperature) which are influenced by the uniqueness of SOI device structure, i.e. the back gate and the floating film body. The model is verified by the good agreement of the simulations with the experimental data. The model is implemented in SPICE2 to be used for circuit and device CAD. Simple SOI CMOS circuits are successfully simulated at different temperatures     

Impact of SOI thickness on device performance and gate oxide reliability of Ni fully silicide metal-gate strained SOI MOSFET

This study investigates the effects of oxide traps induced by SOI of various thicknesses (T_SOI = 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents of the SOI MOSFET devices are also investigated. For devices with high stress (either tensile or compressive) CESL, thinner T_SOI devices have a smaller net remaining stress in gate oxide film than thicker T_SOI devices, and thus possess a smaller bulk oxide trap (N_BOT) and reveal a superior gate oxide reliability. On the other hand, the thicker T_SOI devices show a superior driving capability, but it reveals an inferior gate oxide reliability as well as a larger gate leakage current. From low frequency noise (LFN) analysis, we found that thicker T_SOI device has a higher bulk oxide trap (N_BOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior gate oxide reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker T_SOI devices in this CESL strain technology. In addition, the bending extent of gate oxide film of nMOSFETs is larger than that of pMOSFETs due to the larger net stress in gate oxide film resulting from additional compressive stress of shallow trench isolation (STI) pressed on SOI. Therefore, an appropriate SOI thickness design is the key factor to achieve superior device performance and reliability.     

Improving the reverse recovery of power mosfet integral diodes by electron irradiation

This paper demonstrates that controlled electron irradiation of silicon power MOSFET devices can be used significantly improve the reverse recovery characteristics of their integral reverse conducting diodes without adversely affecting the MOSFET characteristics. By using 3 MeV electron irradiation at room temperature it was found that the reverse recovery charge in the integral diode could be continuously reduced in a well controlled manner from over 500 nC to less than 100 nC without any significant increase in the forward voltage drop of the integral diode under typical operating peak currents. The reverse recovery time was also observed to decrease from 3 microseconds to less than 200 nsec when the radiation dose was increased from 0 to 16 Megarads. The damage produced in gate oxide of the MOSFET due to the electron radiation damage was found to cause an undersirable decrease in the gate threshold voltage. This resulted in excessive channel leakage current flow in the MOSFET at zero gate bias. It was found that this channel leakage current was substantially reduced by annealling the devices at 140°C without influencing the integral diode reverse recovery speed. Thus, the electron irradiation technique was found to be effective in controlling the integral diode reverse recovery characteristics without any degradation of the power MOSFET characteristics.