一种高速片内电流监控器实现

静态电流(IDDQ)测试的实现方法研究是IDDQ测试领域的重要内容之一,高速、高精度是共同追求的目标。通过分析测试向量改变时流过被测电路的电源电流变化情况,得出制约IDDQ测试速度的主要因素。基于此,采用CMOS0.5μm工艺参数、SPICE仿真工具和模拟集成电路设计规则,提出一种快速、高精度的BICS(片内电流监控器)的设计方案。设计中利用辅助的PMOS开关管和延迟电路,有效地解决测试速度问题。设计出的电路达到了100MHz的测试速率、1A测量精度、500mV的最大电源电压降、50μA以上的故障电流检测能力,可以满足一定的实际应用需要。     

CMOS IC漏极静态电流测试技术的现状与发展

全面介绍了CMOS集成电路漏极静态电流(IDDQ)测试技术的现状、应用及其发展趋势。与其它主要用于检测逻辑功能的测试技术不同，IDDQ主要用于检测电路的物理缺陷和工艺故障。作为逻辑功能测试的重要补充，IDDQ技术可提高集成电路的可测性和故障覆盖率，保证集成电路的可靠性。     

用于测试CMOS输出驱动器电流变化率的新电路

提出了一种新的用于测试 CMOS输出驱动器电流变化率的电路结构 .它把片上电感引入到测试系统中作为对实际封装寄生电感的等效 ,从而排除了测试时复杂的芯片 -封装界面的影响 .这种电路结构不仅可以用于实际测算输出驱动器的性能指标 ,还可以用于研究 VL SI电路中的同步开关噪声问题 .该设计方法在新加坡特许半导体公司的 0 .6μm CMOS工艺线上进行了流片验证 .测试结果表明 ,这一测试结构能有效地表征 CMOS输出驱动器的电流变化率的性能指标和 VL SI电路中的同步开关噪声特性     

用于测试CMOS输出驱动器电流变化率的新电路

提出了一种新的用于测试CMOS输出驱动器电流变化率的电路结构．它把片上电感引入到测试系统中作为对实际封装寄生电感的等效,从而排除了测试时复杂的芯片-封装界面的影响．这种电路结构不仅可以用于实际测算输出驱动器的性能指标,还可以用于研究VLSI电路中的同步开关噪声问题．该设计方法在新加坡特许半导体公司的0.6μm CMOS工艺线上进行了流片验证．测试结果表明,这一测试结构能有效地表征CMOS输出驱动器的电流变化率的性能指标和VLSI电路中的同步开关噪声特性．     

裸芯片的IDDQ测试筛选方法研究

IDDQ测试在裸芯片的测试筛选中非常有用，为了获得更高质量与可靠性的产品，许多公司在CMOS生产线中引入了IDDQ测试筛选技术，现在IDDQ测试筛选技术已经作为保证芯片可靠性的重要手段。本文介绍了IDDQ测试筛选技术的重要概念以及其在保证裸芯片可靠性方面的重要作用，并对深亚微米器件中的IDDQ测试筛选方法做了重点介绍。     

CMOS集成电路瞬态电流片外电流传感器电路

瞬态电流(IDDT)测试经常被看作是静态电流(IDDQ)测试的替代或补充,特别在深亚微米技术中,受到越来越多的关注。根据一种基于电荷的瞬态电流片外电流传感器电路,并在其基础上进行改进并对两阶多米诺加法器电路进行仿真实验,实验结果表明,改进后的电路能有效读取集成电路中的瞬态电流,从而实现瞬态电流的测试。     

改进型鉴频鉴相器及电荷泵电路的设计*

本文设计了基于电荷泵架构锁相环电路的两个关键模块—鉴频鉴相器和改进型电流引导电荷泵。基于对扩展鉴相范围和消除死区方法的研究,鉴频鉴相器的性能得以优化。同时,为了保证电荷泵在一个宽输出电压范围内获得良好的电流匹配和较小的电流变化,许多额外的子电路被应用在电路设计中来改进电荷泵的架构。电路采用了标准90 nm CMOS 工艺设计实现并进行测试。鉴频鉴相器鉴相范围的测试结果为-354～354度,改进型电荷泵在0.2～1.1 V的输出电压范围内的电流失配比小于1.1%,泵电流变化小于4%。电路在1.2 V供电电压下的动态功耗为1.3mW。     

一种CMOS蓝牙无线发送器电路

实现了一种低中频架构的CMOS蓝牙无线发送器,提出一种漏极开路输出的功率放大器电路结构.采用0.35 μm数字CMOS工艺制造.测试结果表明:该电路在3.3V电压下总静态电流为19mA;低频的二个DAC,二路低通滤波器和电压/电流转换电路均达到了设计指标;在实现功率控制的同时,完成射频信号的输出.     

一种CMOS蓝牙无线发送器电路

实现了一种低中频架构的CMOS蓝牙无线发送器,提出一种漏极开路输出的功率放大器电路结构.采用0 .35 μm数字CMOS工艺制造.测试结果表明:该电路在3.3V电压下总静态电流为1 9m A;低频的二个DAC,二路低通滤波器和电压/电流转换电路均达到了设计指标;在实现功率控制的同时,完成射频信号的输出     

一种宽动态范围跨阻放大器的设计

针对光电探测器的光电流信号弱、变化范围大的特点,设计了一种全新的检测光电流信号的跨阻放大器(TIA)电路结构,其检测电流信号范围为1.6 μ上A～1.6 mA,动态电流检测范围达到60 dB.通过在电路内部设计出两个增益可调、增益段不同的TIA,分别处理光电流的小电流段(1.6～50 μA)和大电流段(50 μA～1.6 mA),增益可调范围为56～96 dBΩ;通过外置输出电压饱和检测信号,选择所需工作的TIA及其增益段.该电路采用0.18 μm标准CMOS工艺的PDK进行电路设计、版图设计和仿真验证等.测试结果表明:在检测电流为1.6 μA时,输出电压为95 mV;检测电流为1.6mA时,输出电压为915 mV,与仿真结果相一致.电路瞬态特性良好,上升时间为5～10 ns,3.3V电压下功耗小于2 mW,各指标满足设计要求.     

Fault tolerant system based on IDDQ testing

Offline test is essential to ensure good manufacturing quality. However, for permanent or transient faults that occur during the use of the integrated circuit in an application, an online integrated test is needed as well. This procedure should ensure the detection and possibly the correction or the masking of these faults. This requirement of self-correction is sometimes necessary, especially in critical applications that require high security such as automotive, space or biomedical applications. We propose a fault-tolerant design for analogue and mixed-signal design complementary metal oxide (CMOS) circuits based on the quiescent current supply (IDDQ) testing. A defect can cause an increase in current consumption. IDDQ testing technique is based on the measurement of power supply current to distinguish between functional and failed circuits. The technique has been an effective testing method for detecting physical defects such as gate-oxide shorts, floating gates (open) and bridging defects in CMOS integrated circuits. An architecture called BICS (Built In Current Sensor) is used for monitoring the supply current (IDDQ) of the connected integrated circuit. If the measured current is not within the normal range, a defect is signalled and the system switches connection from the defective to a functional integrated circuit. The fault-tolerant technique is composed essentially by a double mirror built-in current sensor, allowing the detection of abnormal current consumption and blocks allowing the connection to redundant circuits, if a defect occurs. Spices simulations are performed to valid the proposed design.     

IDDT Testing versus IDDQ Testing

IDDQ testing has progressed to become a worldwide accepted test method to detect CMOS IC defects. However, it is noticed that observing the average transient current can lead to improvements in real defect coverage, which is referred to IDDT testing. This letter presents a formal procedure to identify IDDT testable faults, and to generate input vector pairs to detect the faults based on Boolean process. It is interesting to note that those faults may not be detected by IDDQ or other test methods, which shows the significance of IDDT testing.     

Compaction of IDDQ Test Sequence Using Reassignment Method

IDDQ testing is an effective method for detecting short faults of CMOS circuits. Since IDDQ testing requires the measurement of current, the testing time of IDDQ testing is longer than that of logical testing. In this paper, we proposed an IDDQ test compaction method for internal short faults of gates in sequential circuits by using the reassignment method of signal values. Experimental results show that test sequences generated by weighted random vectors can be reduced to short sequences with less computation time.     

Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS process

A new charge pump circuit has been proposed to suppress the return-back leakage current without suffering the gate-oxide reliability problem in low-voltage CMOS process. The four-phase clocks were used to control the charge-transfer devices turning on and turning off alternately to suppress the return-back leakage current. A test chip has been implemented in a 65-nm CMOS process to verify the proposed charge pump circuit with four pumping stages. The measured output voltage is around 8.8 V with 1.8-V supply voltage to drive a capacitive output load, which is better than the conventional charge pump circuit with the same pumping stages. By reducing the return-back leakage current and without suffering gate-oxide overstress problem, the new proposed charge pump circuit is suitable for applications in low-voltage CMOS IC products.     

Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing

In this work, IDDQ current for the deep sub-micron VLSI in year 2011 is estimated with a statistical approach according to the International Technology Roadmap for Semiconductors 1999 Edition considering process variations and different input vectors. The estimated results show that the standard deviation of the IDDQ current is proportional to the square root of the circuit size and the IDDQ currents of the defect-free and the defective devices, which are of the size up to 1 × 10⁷ gates, are still differentiable under the condition of random process deviations and input vectors. Two new IDDQ testing schemes, which detect the defective current based on the two separate IDDQ distributions, are proposed. From the study, it is concluded that IDDQ testing is still applicable for the deep sub-micron VLSI for the next ten years.     

The analysis and design of CMOS multidrain logic and stacked multidrain logic

A CMOS logic circuit called the CMOS multidrain logic (MDL) is proposed, analyzed, and experimentally observed. The basic circuit structure, which is derived from integrated injection logic, consists of an enhancement-mode MOSFET as a current injector and a multidrain MOSFET with drain terminals as output nodes and the gate terminal as input node. As compared with the multidrain NMOS logic, the difference is that an enhancement MOS instead of a depletion NMOS is used as a current injector.     

Low‐Voltage Current‐Sensing CMOS Interface Circuit for Piezo‐Resistive Pressure Sensor

A new low‐voltage CMOS interface circuit with digital output for piezo‐resistive transducer is proposed. An input current sensing configuration is used to detect change in piezo‐resistance due to applied pressure and to allow low‐voltage circuit operation. A simple 1‐bit first‐order delta‐sigma modulator is used to produce an output digital bitstream. The proposed interface circuit is realized in a 0.35 µm CMOS technology and draws less than 200 µA from a single 1.5 V power supply voltage. Simulation results show that the circuit can achieve an equivalent output resolution of 9.67 bits with less than 0.23% non‐linearity error.     

A low-power high-speed class-AB buffer amplifier forflat-panel-display application

A low-power, high-speed, but with a large input dynamic range and output swing class-AB output buffer circuit, which is suitable for flat-panel display application, is proposed. The circuit employs an elegant comparator to sense the transients of the input to turn on charging/discharging transistors, thus draws little current during static, but has an improved driving capability during transients. It is demonstrated in a 0.6 μm CMOS technology     

A novel highly accurate current mirror

A novel complementary metal-oxide semiconductor (CMOS) current mirror that can work in weak and strong inversion is proposed. The mirror is capable of accurately copying current in the nano-ampere range. The proposed scheme eliminates the DC matching error caused by the difference between drain-to-source voltages of both the input and output transistors. The proposed circuit was verified using ORCAD simulator in 0.8 μm CMOS process technology. Simulation results confirm the functionality and accuracy of the circuit.     

An on-chip 96.5% current efficiency CMOS linear regulator using aflexible control technique of output current

This paper proposes an on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current (FCOC). By the use of the FCOC technique, the proposed circuit realizes flexible output current drive according to the load current variation. Therefore, the proposed linear regulator ran supply stable output voltage using the FCOC technique. The linear regulator is fabricated by double-metal 1.2-μm CMOS technology. The number of transistors is 46 and the die size is 0.423 mm². The fabricated linear regulator achieves a fluctuation of output voltage less than 6.81 mV_p-p at a frequency of output current f(I_out) ranging from 1.8 Hz to 100 MHz. Moreover, the fabricated on-chip CMOS linear regulator can achieve 96.5% current efficiency