共查询到19条相似文献,搜索用时 89 毫秒
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张海鹏 汪沁 孙玲玲 高明煜 李文钧 吕幼华 刘国华 汪洁 Zhang Haipeng Wang Qin Sun Lingling Gao Mingyu Li Wenjun Lü Youhua Liu Guohua Wang Jie 《半导体学报》2006,27(z1):279-282
为探索与国内VLSI制造工艺兼容的新型SOI LIGBT/LDMOS器件与PIC的设计理论和工艺实现方法,首次提出含有抗ESD二极管的集成SOI LIGBT/LDMOS器件截面结构和版图结构,并根据器件结构给出了阻性负载时器件的大信号等效电路.探讨了该结构器件的VLSI工艺实现方法,设计了工艺流程.讨论了设计抗ESD二极管相关参数所需考虑的主要因素,并给出了结构实现的工艺控制要求. 相似文献
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提出了一种具有叠层埋氧层的新栅型绝缘体上硅(SOI)器件。针对SOI器件的抗总电离剂量(TID)加固方案,对绝缘埋氧层(BOX)采用了叠层埋氧方案,对浅沟槽隔离(STI)层采用了特殊S栅方案。利用Sentaurus TCAD软件,采用Insulator Fixed Charge模型设置固定电荷密度,基于0.18μm CMOS工艺对部分耗尽(PD)SOI NMOS进行了TID效应仿真,建立了条栅、H栅、S栅三种PD SOI NMOS器件的仿真模型。对比三种器件辐照前后的转移特性曲线、阈值电压漂移量、跨导退化量,验证了该器件的抗TID辐照性能。仿真结果表明,有S栅的器件可以抗kink效应,该PD SOI NMOS器件的抗TID辐照剂量能力可达5 kGy。 相似文献
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SOI工艺下NMOS管的热载流子效应研究 总被引:2,自引:2,他引:0
摘要:本文研究了SOI工艺下环形栅NMOS和双边栅NMOS(H型栅NMOS、T型栅NMOS和普通条形栅NMOS)的热载流子效应。基于热载流子退化的化学反应方程式和一种与器件几何结构相关的反应扩散方程,提出了环形栅NMOS和双边栅NMOS的热载流子退化模型。根据此模型得出,热载流子退化的时间指数与NMOS的栅结构密切相关,且环形栅NMOS与双边栅NMOS相比,热载流子退化更加严重。通过对0.5 PD SOI 工艺下这几种不同栅结构的NMOS管的设计、流片和热载流子试验,验证了结论。 相似文献
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对高压13CD--MOS器件的结构和工艺进行了研究,用器件模拟MEDICI和工艺模拟T-SUPREM软件分别对器件结构和工艺参数进行了设计优化.在工艺兼容的前提下,设计制作了包含NPN、PNP、NMOS、PMOS、高压LDMOS等结构的BCDMOS集成电路样管.测试结果表明,样管性能与模拟结果相符. 相似文献
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为了在薄埋氧层SOI衬底上实现超高耐压LDMOS铺平道路,提出了一种具有P埋层(BPL)的薄埋氧层SOI LDMOS 结构,耐压1200V以上.该BPL SOI LDMOS在传统SOI LDMOS的埋氧层和N型漂移区之间引入了一个P型埋层.当器件正向截止时,N型漂移区与P埋层之间的反偏PN结将承担器件的绝大部分纵向压降.采用2维数值仿真工具Silvaco TCAD对BPL SOI LDMOS进行虚拟制造和器件仿真,结果表明该结构采用适当的参数既能实现1 280 V的耐压,将BOL减薄到几百纳米以下又可以改善其热特性. 相似文献
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High-temperature off-state characteristics of thin-SOI RESURF LDMOS transistors were studied experimentally and theoretically and compared with off-state characteristics of junction-isolated bulk-Si power devices. At 200°C, the off-state leakage current in the SOI devices was approximately 200 times lower than in the bulk-Si devices with a comparable breakdown voltage and on-resistance. At 300°C, well beyond the operating range of the bulk devices, the off-state leakage current in the SOI devices was only 1.5 nA/μm. The leakage current appears to scale with the thickness of the SOI layer. The results of this study indicate that LDMOS transistors fabricated in thin SOI layers are well suited for high-temperature power IC applications 相似文献
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《Electron Device Letters, IEEE》2006,27(11):917-919
In this letter, a CMOS-compatible silicon-on-insulator (SOI) RF laterally diffused MOS (LDMOS) technology is proposed based on TiSi2 salicide with SiO2/Si3N4 dual sidewalls. The use of dual sidewalls yields a large process margin for defining drift regions and preventing source-gate silicide bridging. This technology improves the cutoff frequencies and the maximum oscillation frequencies by 27%-42% and 14%-22%, respectively, for a gate length in the range of 0.5-0.25 mum. For the shortest 0.25-mum gate length, a record cutoff frequency of 19.3 GHz and a high breakdown voltage of 16.3 V are achieved simultaneously for SOI RF LDMOS. This LDMOS technology is suitable for 3.6-V-supply 0-3-GHz power RFIC applications 相似文献
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SiGe BiCMOS technology for RF circuit applications 总被引:4,自引:0,他引:4
SiGe BiCMOS is reviewed with focus on today's production 0.18-/spl mu/m technology at f/sub T//f/sub MAX/ of 150/200 GHz and future technology where device scaling is bringing about higher f/sub T//f/sub MAX/, as well as lower power consumption, noise figure, and improved large-signal performance at higher levels of integration. High levels of radio frequency (RF) integration are enabled by the availability of a number of active and passive modules described in this paper including high voltage and high-power devices, complementary PNPs, high quality MIM capacitors, and inductors. Key RF circuit results highlighting the advantages of SiGe BiCMOS in addressing today's RF IC market are also discussed both for applications at modest frequencies (1 to 10 GHz) as well as for emerging applications at higher frequencies (20 to >100 GHz). 相似文献
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This paper describes a SOI LDMOS/CMOS/BJT technology that can be used in portable wireless communication applications. This technology allows the complete integration of the front-end circuits with the baseband circuits for low-cost/low-power/high-volume single-chip transceiver implementation. The LDMOS transistors (0.35 μm channel length, 3.8 μm drift length, 4.5 GHz fT and 21 V breakdown voltage), CMOS transistors (1.5 μm channel length, 0.8/-1.2 V threshold voltage), lateral NPN transistor (18 V BVCBO and h FE of 20), and high Q-factor (up to 6.1 at 900 MHz and 7.2 at 1.8 GHz) on-chip inductors are fabricated. A fully-functional high performance integrated power amplifier for 900 MHz wireless transceiver application is also demonstrated 相似文献
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功率集成器件在交流转直流(AC/DC)电源转换IC、高压栅驱动IC、LED驱动IC等领域均有着广泛的应用。介绍了典型的可集成功率高压器件,包括不同电压等级的横向双扩散金属氧化物半导体场效应晶体管(LDMOS)以及基于硅和SOI材料的横向绝缘栅双极型晶体管(LIGBT),此外还介绍了高低压器件集成的BCD工艺和其他的功率集成关键技术,包括隔离技术、高压互连技术、dV/dt技术、di/dt技术、抗闩锁技术等,最后讨论了功率集成器件及其兼容技术的发展趋势。 相似文献
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提出了具有n埋层PSOI(部分SOI)结构的射频功率LDMOS器件.射频功率LDMOS的寄生电容直接影响器件的输出特性.具有n埋层结构的PSOI射频LDMOS,其Ⅰ层下的耗尽层宽度增大,输出电容减小,漏至衬底的结电容比常规LDMOS和PSOI LDMOS分别降低39.1%和26.5%.1dB压缩点处的输出功率以及功率增益比PSOI LDMOS分别提高62%和11.6%,附加功率效率从34.1%增加到37.3%.该结构器件的耐压比体硅LDMOS提高了14%. 相似文献