2.4GHz低噪声放大器的全芯片ESD保护设计

设计并流片验证了一种0.18μmRFCMOS工艺的2.4GHz低噪声放大器的全芯片静电放电(ESD)保护方案。对于射频(RF)I/O口的ESD防护,主要对比了二极管、可控硅(SCR)以及不同版图的互补型SCR,经流片与测试,发现岛屿状互补型SCR对I/O端口具有很好的ESD防护综合性能。对于电源口的ESD防护,主要研究了不同触发方式的ESD保护结构,结果表明,RCMOS触发SCR结构(RCMOS-SCR)具有良好的ESD鲁棒性和开启速度。基于上述结构的全芯片ESD保护设计,RF I/O口采用岛屿状布局的互补SCR结构的ESD防护设计,该ESD防护电路引入0.16dB的噪声系数和176fF的寄生电容,在人体模型(HBM)下防护能力可达6kV;电源口采用了RCMOS-SCR,实现了5kV HBM的ESD保护能力,该设计方案已经在有关企业得到应用。     

射频电路ESD防护优化设计

在0.18 μm SiGe BiCMOS工艺下,设计了三种射频端口的ESD防护电路。在不影响ESD防护能力的前提下,通过串联多级二极管,可以显著提高射频电路的线性度。通过在二极管通路中串联LC谐振网络和大电感,在显著降低射频端口ESD防护电路插入损耗的同时还提高了射频电路的线性度。仿真结果表明,两级串联二极管结构可以将输入1 dB压缩点提高至18.9 dBm。在16 GHz频点,串联LC谐振网络设计和串联大电感设计分别可以将插入损耗减小0.5 dB和0.9 dB。     

与Si 工艺兼容的Si/ SiGe/ Si HBT 研究

我们对Si/SiGe/Si HBT及其Si兼容工艺进行了研究,在研究了一些关键的单项工艺的基础上,提出了五个高速Si/SiGe/Si HBT结构和一个低噪声Si/SiGe/Si HBT结构,并已研制成功台面结构Si/SiGe/Si HBT和低噪声Si/SiGe/Si HBT,为进一步高指标的Si/SiGe/Si HBT的研究建立了基础。     

射频Si/SiGe/Si HBT的研究

在Si／SiGe／SiHBT与Si工艺兼容的研究基础上，对射频Si／SiGe／SiHBT的射频特性和制备工艺进行了研究，分析了与器件结构有关的关键参数寄生电容和寄生电阻与Si／SiGe/Si HBT的特征频率fT和最高振荡频率fmax的关系，成功地制备了fT为2．5CHz、fmax为2．3GHz的射频Si／SiGe／SiHBT，为具有更好的射频性能的Si／SiGe／Si HBT的研究建立了基础。     

基于130 nm SOI工艺数字ASIC ESD防护设计

绝缘体上硅(SOI)工艺具有寄生电容小、速度快和抗闩锁等优点,成为低功耗和高性能集成电路(IC)的首选.但SOI工艺IC更易受自加热效应(SHE)的影响,因此静电放电(ESD)防护设计成为一大技术难点.设计了一款基于130 nm部分耗尽型SOI (PD-SOI)工艺的数字专用IC (ASIC).针对SOI工艺ESD防护设计难点,进行了全芯片ESD防护原理分析,通过对ESD防护器件、I/O管脚ESD防护电路、电源钳位电路和ESD防护网络的优化设计,有效减小了SHE的影响.该电路通过了4.5 kV人体模型ESD测试,相比国内外同类电路有较大提高,可以为深亚微米SOI工艺IC ESD防护设计提供参考.     

SiGe HBT瞬时剂量率效应实验及仿真研究

锗硅异质结双极晶体管(SiGe Heterojunction Bipolar Transistor,SiGe HBT)由于其优异的温度和频率特性,在航空航天等极端环境中具有良好的使用前景,其辐射效应得到了广泛关注。针对KT9041 SiGe HBT进行了瞬时γ射线及脉冲激光辐照实验,获得其瞬时剂量率效应(Transient Dose Rate Effect,TDRE)响应。实验结果表明,SiGe HBT收集极在辐照下会产生明显的光电流脉冲,并且存在着饱和阈值的现象。此外,在脉冲激光辐照实验中还进行了SiGe HBT总剂量效应与瞬时剂量率效应的协同效应研究。发现SiGe HBT在经过总剂量辐照后其产生的光电流幅值会变大。为了分析实验中观察到的现象,应用TCAD建立了KT9041 SiGe HBT的仿真模型,并进行了瞬时γ射线辐照以及总剂量效应仿真研究。仿真发现,SiGe HBT收集极光电流出现的饱和现象是由示波器端口50 Ω匹配电阻所造成的。而总剂量效应导致的光电流幅值变大则是由于总剂量效应会在SiGe HBT收集极电极处的Si/SiO₂界面引入正电荷缺陷,正电荷缺陷产生的局部电场会对自由电子产生吸引作用,导致更多的自由电子被收集极收集,从而产生幅值更大的光电流。     

锗硅异质结双极晶体管空间辐射效应研究进展

异质结带隙渐变使锗硅异质结双极晶体管(SiGe HBT)具有良好的温度特性,可承受-180~+200 ℃的极端温度,在空间极端环境领域具有诱人的应用前景。然而,SiGe HBT器件由于材料和工艺结构的新特征,其空间辐射效应表现出不同于体硅器件的复杂特征。本文详述了SiGe HBT的空间辐射效应研究现状,重点介绍了国产工艺SiGe HBT的单粒子效应、总剂量效应、低剂量率辐射损伤增强效应以及辐射协同效应的研究进展。研究表明,SiGe HBT作为双极晶体管的重要类型,普遍具有较好的抗总剂量和位移损伤效应的能力,但单粒子效应是制约其空间应用的瓶颈问题。由于工艺的不同,国产SiGe HBT还表现出显著的低剂量率辐射损伤增强效应响应和辐射协同效应。     

SiGe BiCMOS技术发展现状

以通讯领域的需求和技术发展为背景,介绍了SiGe HBT器件以及SiGe BiCMOS技术的发展历程。总结了SiGe HBT器件在器件结构和工艺步骤上的共同点。以IBM公司0.5μmSiGe BiCMOS为例,介绍了SiGe BiCMOS典型工艺步骤,分析了BDG和BAG两种工艺集成方式在不同技术节点上应用的利弊。最后,以捷智半导体和IBM产品线为例,对SiGe HBT器件以及SiGe BiCMOS技术划分技术节点。     

微波功率SiGe HBT研究进展

Si的热导率比大部分化合物半导体(如GaAs)的热导率高,SiGe HBT在一个较宽的温度范围内稳定,SiGe HBT的发射结电压VBE的温度系数dVBE/dT比Si的小,双异质结SiGe HBT本身具有热-电耦合自调能力,所加镇流电阻可以较小,所有这些使SiGe HBT比GaAs HBT和SiBJT在功率处理能力上占一定优势。文章对微波功率SiGe HBT一些重要方面的国内外研究进展进行评述,希望对从事微波功率SiGe HBT的研究者有所帮助。     

SiGe HBT低噪声放大器的设计与制造

该文设计和制作了一款单片集成硅锗异质结双极晶体管(SiGe HBT)低噪声放大器(LNA)。由于放大器采用复合型电阻负反馈结构,所以可灵活调整不同反馈电阻,同时获得合适的偏置、良好的端口匹配和低的噪声系数。基于0.35 m Si CMOS平面工艺制定了放大器单芯片集成的工艺流程。为了进一步降低放大器的噪声系数,在制作放大器中SiGe器件时,采用钛硅合金(TiSi2)来减小晶体管基极电阻。由于没有使用占片面积大的螺旋电感,最终研制出的SiGe HBT LNA芯片面积仅为0.282 mm2。测试结果表明,在工作频带0.2-1.2 GHz内,LNA噪声系数低至2.5 dB,增益高达26.7 dB,输入输出端口反射系数分别小于-7.4 dB和-10 dB。     

Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process

Electrostatic discharge (ESD) protection design for high-speed input/output (I/O) interface circuits in a 130-nm CMOS process is presented in this paper. First, the ESD protection diodes with different dimensions were designed and fabricated to evaluate their ESD levels and parasitic effects in gigahertz frequency band. With the knowledge of the dependence of device dimensions on ESD robustness and the parasitic capacitance, whole-chip ESD protection scheme were designed for the general receiver and transmitter interface circuits. Besides, an ESD protection scheme is proposed to improve the ESD robustness under the positive-to-V_SS (PS-mode) ESD test, which is the most critical ESD-test pin combination. With a silicon-controlled rectifier (SCR) between the I/O pad and V_SS, the clamping voltage along the PS-mode ESD current path can be reduced, so the PS-mode ESD level can be improved. Besides, the parasitic P-well/N-well diode in the SCR can provide the NS-mode ESD current path. Thus, SCR is the most promising ESD protection device in ESD protection design with low-capacitance consideration. The ESD protection scheme presented in this paper has been practically applied to an IC product with 2.5-Gb/s high-speed front-end interface.     

ESD protection design considerations for InGaP/GaAs HBT RF power amplifiers

In order to design a robust electrostatic discharge (ESD) protected RF amplifier in InGaP/GaAs HBTs, a comprehensive assessment of device vulnerability to ESD events in both active transistors and passive components of the HBT technology is presented in this paper. The results include not only the intrinsic HBT's ESD robustness performance, but also its dependence on device layout, ballast resistor, and process. Acknowledging the ESD constraints imposed on InGaP/GaAs HBT technology, a 5.4-6.0-GHz power amplifier (PA) with a compact 2000 V/sub ESD/ (human body model) on-chip ESD protection circuit that has a low loading capacitance of less than 0.1 pF and that does not degrade RF and output power performance is developed for wireless local area network application. A diode triggered Darlington pair is implemented as the ESD protection circuit instead of the traditional diode string. Its operation principle, ESD protection performance, and PA performance are also illustrated in this paper.     

Characterization Analysis of UDSM LVTSCR Under TLP Stress

The characteristics of a low-voltage triggering silicon-controlled rectifier (LVTSCR) under a transmission line pulse (TLP) and the characteristics of high frequency are analyzed. The research results show that the anode series resistance has a significant effect on the key points of the snapback curve. The device characteristics can fit the requirements of a electrostatic discharge (ESD) design window by adjusting the anode series resistance. Furthermore, the set-up time of the ESD has an influence on the turn-on voltage of the LVTSCR. A steep rising edge will cause the turn-on voltage to increase. The parasitic capacitance of the device for different voltage biases and frequencies determines the capacitive impedance, and its accuracy calculation is very important to the ESD design of high frequency circuits. Our research results provide a theoretical basis for the design of an ultra-deep sub-micron (UDSM) LVTSCR structure under ESD stress and the improvement of TLP test technology.     

Insight into multiple-triggering effect in DTSCRs for ESD protection

The diode-triggered silicon-controlled rectifier (DTSCR) is widely used for electrostatic discharge (ESD) protection in advanced CMOS process owing to its advantages, such as design simplification, adjustable trigger/holding voltage, low parasitic capacitance. However, the multiple-triggering effect in the typical DTSCR device may cause undesirable larger overall trigger voltage, which results in a reduced ESD safe margin. In previous research, the major cause is attributed to the higher current level required in the intrinsic SCR. The related discussions indicate that it seems to result from the current division rule between the intrinsic and parasitic SCR formed in the triggering process. In this letter, inserting a large space into the trigger diodes is proposed to get a deeper insight into this issue. The triggering current is observed to be regularly reduced along with the increased space, which confirms that the current division is determined by the parasitic resistance distributed between the intrinsic and parasitic SCR paths. The theoretical analysis is well confirmed by device simulation and transmission line pulse (TLP) test results. The reduced overall trigger voltage is achieved in the modified DTSCR structures due to the comprehensive result of the parasitic resistance vs triggering current, which indicates a minimized multiple-triggering effect.     

A new on-chip ESD protection circuit with dual parasitic SCRstructures for CMOS VLSI

A new CMOS on-chip electrostatic discharge (ESD) protection circuit which consists of dual parasitic SCR structures is proposed and investigated. Experimental results show that with a small layout area of 8800 μ², the protection circuit can successfully perform negative and positive ESD protection with failure thresholds greater than ±1 and ±10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. The low ESD trigger voltages in both SCRs can be readily achieved through proper circuit design and without involving device or junction breakdown. The input capacitance of the proposed protection circuit is very low and no diffusion resistor between I/O pad and internal circuits is required, so it is suitable for high-speed applications. Moreover, this ESD protection circuit is fully process compatible with CMOS technologies     

ESD protection design for 1- to 10-GHz distributed amplifier in CMOS technology

Two distributed electrostatic discharge (ESD) protection schemes are presented and applied to protect distributed amplifiers (DAs) against ESD stresses. Fabricated in a standard 0.25-/spl mu/m CMOS process, the DA with the first protection scheme of the equal-sized distributed ESD (ES-DESD) protection scheme, contributing an extra 300 fF parasitic capacitance to the circuit, can sustain the human-body model (HBM) ESD level of 5.5 kV and machine-model (MM) ESD level of 325 V and exhibits the flat-gain of 4.7 /spl plusmn/ 1 dB from 1 to 10 GHz. With the same amount of parasitic capacitance, the DA with the second protection scheme of the decreasing-sized distributed ESD (DS-DESD) protection scheme achieves better ESD robustness, where the HBM ESD level over 8 kV and MM ESD level is 575 V, and has the flat-gain of 4.9 /spl plusmn/ 1.1 dB over the 1 to 9.2-GHz band. With these two proposed ESD protection schemes, the broad-band RF performances and high ESD robustness of the DA can be successfully codesigned to meet the application specifications.     

功率VDMOS器件的ESD瞬态模型

基于对功率VDMOS器件ESD保护及初始条件的分析,建立了VDMOS器件的ESD保护等效电路,分析了ESD响应过程,得到功率VDMOS器件的ESD瞬态模型. 分析结果表明,该模型准确地描述了功率VDMOS器件的ESD瞬态放电过程,解决了以往模型中初始条件分析不足等问题. 借助该模型,获得ESD器件的等效电阻和击穿电压、VDMOS的栅极输入电阻、栅源电容、栅氧厚度等与功率VDMOS器件抗ESD能力的关系,为功率VDMOS器件的抗ESD保护设计提供重要指导.     

ESD protection design on analog pin with very low input capacitancefor high-frequency or current-mode applications

An electrostatic discharge (ESD) protection design is proposed to solve the ESD protection challenge to the analog pins: for high-frequency or current-mode applications, By including an efficient power-rails clamp circuit in the analog input/output (I/O) pin, the device dimension (W/L) of an ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the human body model (HBM) and machine model (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only ~1.0 pF (including the bond-pad capacitance) for high-frequency applications     

Design and Analysis of On-Chip ESD Protection Circuit with Very Low Input Capacitance for High-Precision Analog Applications

An ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (m/m) in a 0.35-m silicided CMOS process, but it can sustain the human-body-model (machine-model) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only 1.0 pF (including the bond pad capacitance) for high-frequency applications. A design model to find the optimized layout dimensions and spacings on the input ESD clamp devices has been also developed to keep the total input capacitance almost constant (within 1% variation), even if the analog input signal has a dynamic range of 1 V.     

一种用于提高ESD保护器件开启速度的新型变化横向基区 掺杂结构双触发晶闸管

The turn-on speed of electrostatic discharge （ESD） protection devices is very important for the protection of the ultrathin gate oxide. A double trigger silicon controlled rectifier device （DTSCR） can be used effectively for ESD protection because it can turn on relatively quickly. The turn-on process of the DTSCR is first studied, and a formula for calculating the turn-on time of the DTSCR is derived. It is found that the turn-on time of the DTSCR is determined mainly by the base transit time of the parasitic p-n-p and n-p-n transistors. Using the variation lateral base doping （VLBD） structure can reduce the base transit time, and a novel DTSCR device with a VLBD structure （VLBD_DTSCR） is proposed for ESD protection applications. The static-state and turn-on characteristics of the VLBD DTSCR device are simulated. The simulation results show that the VLBD structure can introduce a built-in electric field in the base region of the parasitic n-p-n and p--n-p bipolar transistors to accelerate the transport of free-carriers through the base region. In the same process and layout area, the turn-on time of the VLBD DTSCR device is at least 27% less than that of the DTSCR device with the traditional uniform base doping under the same value of the trigger current.