高功率雷达空间功率合成效率研究

高功率微波空间功率合成效率直接关系到高功率雷达输出功率的大小,重点研究高功率雷达空间功率合成效率问题。首先推导出高功率微波空间合成效率公式;然后分析了影响合成效率的相位误差、目标位置误差、时延误差和阵元间距误差等因素;最后提出一种幅度-相位联合调整的方法,通过增加幅度调整电路和相位调整电路,减小通道的幅相误差,提高空间功率合成效率。     

An efficient X-band 16-element spatial combiner of switched-mode power amplifiers

This paper describes the design, implementation, and characterization of a high-efficiency 10-GHz amplifier antenna array for spatial power combining. An average drain efficiency of 70% at 162 W effective isotropic radiated power, or about 1.5 W of transmitted power, is measured for an array of 16 amplifiers consisting of four four-element subarrays. The power-combining efficiency of the 16-element array is above 79%. The active device is a low-cost GaAs MESFET with a maximum available power in class A of 21 dBm. The single class-E power amplifier delivers 20.3 dBm with 67% drain efficiency and 58% power-added efficiency.     

水声扩频信号发射机的研究

设计了大功率水声扩频信号发射机,该发射机具有调制方式多样,效率高,功率大,体积小等特点,并给出了发射机硬件的电路设计和软件控制程序实现过程。本扩频信号发射机采用ARM7 LPC2378作为主控芯片进行编码计算后输出扩频基带信号,采用直接数字式频率合成器(DDS)完成扩频信号的调制输出。根据全桥拓扑功率电路和绝缘栅双极性晶体管(IGBT)功率管的特点,设计了扩频信号发射机的功放输出电路。最后,对该扩频信号发射机的输出功率进行了实验验证,结果表明整机电路设计完全达到设计要求。     

脉冲行波管发射机功率合成技术的研究

一种提高发射源射频功率的有效方法是采用空间功率合成技术,应用多部子阵发射单元作为馈源,通过相控阵技术在空间合成获得远高于单管发射机射频能量,发射机功率合成技术是实现空间功率合成关键技术,要求射频源在宽带内具有高的幅相稳定,各子阵发射机在宽带内要求幅相一致。文中介绍了一种工程化的脉冲行波管功率合成体制的发射机,分析了提高发射机幅相性能的技术问题,进行了功率合成效率分析,给出了发射机主要试验结果,对其广阔的应用前景作出了展望。     

锂离子电池的保护芯片设计

设计了一种基于CMOS工艺的锂离子电池保护芯片,采用工作在亚阈值区的电路结构,使电路具有高效低耗的特点,能够防止电池在工作过程中出现过充电、过放电、过电流和短路等异常状态。模拟结果表明,该芯片实现了基本保护功能并在功耗方面达到了设计目标。     

A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor

A 4-MB L2 data cache was implemented for a 64-bit 1.6-GHz SPARC(r) RISC microprocessor. Static sense amplifiers were used in the SRAM arrays and for global data repeaters, resulting in robust and flexible timing operation. Elimination of the global clock grid over the SRAM array saves power, enabled by combining the clock information with array select signals. Redundancy was implemented flexibly, with shift circuits outside the main data array for area efficiency. The chip integrates 315 million transistors and uses an 8-metal-layer 90-nm CMOS process.     

高效功率合成电路及其分析方法

本文阐明当功率放大器幅、相不一致或部分动放不工作时，仍有高合成效率的新型功率合成电路。以有四个功放的合成电路为例，给出有关电路参数并介绍其分析方法。     

28 GHz omni-directional quasi-optical transmitter array

Omni-directional base stations are needed in many emerging wireless communication systems. This paper presents the first adaptation of a quasi-optical oscillator array for this purpose. A 28 GHz active oscillator element containing a modified Vivaldi endfire antenna is utilized as the unit cell. Twelve of these are incorporated into the circular array, which is powered from a single DC power supply. The array has a high combining efficiency and remains frequency-locked over a span of 600 MHz     

工作在1.8-3 GHz内的高效率GaAs pHEMT功率单片

本文报道了一款基于南京电子器件研究所GaAs pHEMT单片集成电路工艺的S波段宽带高效率功率放大器。为了提高芯片效率,该放大器采用驱动比为1:8的两级级联方式,并采用低通/高通滤波器相结合的拓扑结构设计每级的匹配电路。这种匹配电路在有效降低芯片面积的同时,在较宽的频带范围内实现对应于高效率的阻抗匹配。在5V漏压AB类偏置条件下,该功率放大器在1.8到3GHz频率范围内连续波输出饱和功率为33~34 dBm,相应的附加效率达到35%~45%,以及非常平坦的功率增益25~26 dB。芯片面积紧凑,尺寸仅为2.7mm×2.75mm。     

基于PSoC的超声相控阵高精度测距系统的研究

基于传统的超声相控阵测距系统设计了一种新型测距系统。该系统采用Cypress公司所生产的嵌入式芯片PSoC5为主控制器,其丰富的内部功能模块完全能够满足系统的设计需求。与传统的超声相控阵测距系统相比,该系统节约PCB硬件资源,提高设计效率,降低功耗。实验研究表明,该测距系统具有指向性强,精确度高的特点。     

40Gbit／s高速并行12信道光接收模块的研制

研究并制作了12信道并行光接收模块,单信道传输速率大于等于3．318Gbit／s,12信道并行总传输速率为40Gbit／s。模块采用工作波长在850nm的高速PIN型光电探测器（PD）列阵作为光接收器件,PD列阵与接收电路芯片直接用Au丝压焊连接,输入光信号直接由12信道的光纤阵列耦合进入PD列阵中。对光接收模块进行眼...     

稀疏阵列时间反演脉冲信号空间功率合成方法

时间反演电磁波具有时空二维同步聚焦特性.基于时间反演电磁波原理建立了稀疏阵列脉冲信号相干合成的数学模型, 通过理论分析与蒙特卡洛实验相结合的方法研究了合成信号幅度最大时刻目标点合成效率值的统计特征与相位误差及阵元数的关系.分析表明, 在工程实践中, 除尽可能提高相控精度外, 可以通过增加阵列的阵元数来减小目标点合成效率的方差, 以降低相控误差的影响.利用仿真计算研究了相位误差及信号形式对时间反演脉冲信号合成效果的影响, 证实了稀疏阵列时间反演脉冲信号空间功率合成的可行性; 分析方法和结果可以为工程实践中如何折衷需求与条件确定相位误差的控制精度提供理论依据.     

Quasi-optical 150-GHz power combining oscillator

A quasi-optical power combiner for a five-element in-line oscillator array is experimentally investigated at 150 GHz. The combiner consists of a periodic dielectric phase grating (hologram) which transforms the near-field of a rectangular horn antenna array into a pseudo-plane wave. The horn array is excited by IMPATT oscillators operating uniformly in both amplitude and phase. A dual offset reflector set-up transforms the pseudo-plane wave to a Gaussian beam which matches the field pattern of a dual mode receiving antenna. Even though an inter-element spacing of 9.5 /spl lambda/ has been chosen, the passive structure gives a power combining efficiency of 74.1%. The power combining oscillator has been operated in both free-running and injection-locked mode. A CW output power of 78.0 mW and 83.5 mW was measured for the free-running and injection-locked oscillator, respectively, which is corresponding to a power combining efficiency of 66.5% and 71.2%, respectively.     

New technique for combining solid-state sources

The advent of many new moderate power solid-state devices has created a renewed interest in the techniques for combining these devices to achieve even higher powers. This paper describes a new technique for combining large numbers of energy sources by using a dense array of radiating elements. The impedance of the radiating elements, as determined theoretically and confirmed using an array simulator, may be well mat to parallel one hundred transistor amplifiers has a net gain of 4.75 dB at 410 MHz with 100-watts output. Tests in which individual failures were simulated indicate that array elements were well isolated from each other.     

A digitally controlled DC/DC converter for an RF power amplifier

This paper describes design and implementation of a digitally controlled dc/dc converter that provides a dynamically adjustable supply voltage for a radio frequency power amplifier (RFPA). The techniques employed in the design include a combination of constant-frequency continuous conduction mode (CCM) and a variable-frequency discontinuous conduction mode to achieve very high converter efficiency over a wide range of output power levels. The variable-frequency converter control is accomplished using a current-estimator circuit, which eliminates the need for current sensing. A field-programmable gate array (FPGA)-based digital controller implementation allows programmability of the mode transition and other controller parameters. In the complete experimental system, which consists of the digitally controlled dc/dc converter and a class-E RFPA operating at 10GHz, experimental results show that the overall system efficiency is significantly improved over a wide range of RFPA output power levels.     

基于RapidIO的相控阵短波发信系统交换单元设计

传统总线技术成为了制约短波通信系统性能进一步提升的瓶颈。RapidIO总线是一种新型嵌入式总线,具有传输效率高、系统成本低、系统稳定性好等特点。基于RapidIO技术设计了相控阵短波发信系统的交换单元,硬件上进行了系统供电电路、时钟电路和交换芯片端口电路设计;软件上主要介绍了RapidIO初始化和交换芯片的远程配置两个方面。在实际应用中实现了系统中各模块间信号的高速交换。     

A 16-kbit block addressed charge-coupled memory device

This paper describes the design and performance of a 16- kbit charge-coupled serial memory device. The memory is organized in four blocks of 4 kbits each with on-chip decoding and is mounted in a 16-pin ceramic dual-in-line hermetic package. Each 4-kbit block is organized as a serial-parallel-serial (SPS) array. Operated at a data rate of 1 MHz the mean access time is 2 ms and the on-chip power dissipation is calculated to be 1.5 µW/bit with another 0.5 µW/bit being required in off-chip clock drivers. The maximum designed output data rate is 10 MHz. Compared to the serpentine and loop organized memory charge-coupled device (CCD), the SPS organization has the advantages of lower power dissipation, greater tolerance to process parameter variations, and higher output data rate. All inputs and outputs are TTL compatible. Write/recirculate control is provided on the chip as well as two-dimensional decoding to permit memory matrix organization with X, Y chip select control. All the on-chip peripheral circuits use dynamic MOS circuitry to minimize power consumption. The charge sensing on the chip is achieved with balanced regenerative sense amplifiers. The memory array uses the three-phase three-level polysilicon electrode structure, and the chip is fabricated using an MOS n-channel polysilicon gate process with self-aligned source, drain, and channel stop.     

功能可配置的数字变频芯片的研制与测试

为满足数字相控阵雷达对收发通道关键元器件国产化的需求,基于国内工艺线研制了一款数字变频芯片。该芯片包含双通道的数字下变频(DDC)与数字上变频(DUC)电路,通过LVDS 接口与SPI接口实现与上位机的数据交换。该芯片的抽取率/ 插值率、数字本振频率、相位偏置、通道幅度补偿系数、滤波器系数等参数均可配置,能够适应不同工作场景。通过修改数字变频器中数控振荡器(NCO)的相位偏置,可以实现对收发信号的移相操作,使与本芯片配对使用的TR组件可以取消移相器。通过门控时钟等低功耗设计大大降低了该芯片的平均功耗,减轻了供电与散热压力。经过芯片测试,该芯片的DDC与DUC的通带纹波<0. 05 dB,阻带衰减>70 dBc,平均功耗<1. 2 W,其功能与性能满足系统应用,为相控阵雷达收发通道的小型化与国产化提供了新的解决方案。     

多芯片阵列组合白光LED封装研究

文章阐述了LED器件的发光原理和芯片电极结构,围绕白光HB-LED的封装工艺,设计单个大功率芯片封装结构并对整个封装工艺进行研究,提出了多芯片阵列组合封装的创新理念,将其应用于多芯片阵列封装模块中。得出HB-LED封装中关键技术问题是提高外量子效率,采用高折射率硅胶减少折射率物理屏障带来的光子损失;采用高热导率的材料,减少由于封装工艺的缺陷带来的界面热阻。     

基于微透镜阵外腔的光纤激光谱组束耦合效率分析

为了克服光纤激光外腔谱组束系统中增益带宽和透镜像差对组束阵元数量的限制,在系统中加入了微透镜阵。根据光束变换理论,建立了基于微透镜阵的光纤激光外腔谱组束系统的外腔耦合效率分析模型。通过数值模拟,对各种相关参数对耦合效率的影响进行了仿真分析。结果表明:微透镜阵的加入极大提高了阵元的耦合效率和系统的组束潜力;为了获得尽可能高的耦合效率,需要对离焦量进行合理配置并设计具有较长焦距的微透镜;横向对准误差是影响耦合效率的主要因素,对于宽度为10 mm的组束光纤阵列,为保证60%以上的耦合效率,在θy≤2 mrad的同时需将横向位置偏移量δy限制在10μm以内。