一种基于BSIM-CMG的FinFET变容管模型

提出了一种适用于FinFET变容管的建模方法.在BSIM-CMG的基础上,模型采用衬底模型和外围寄生模型来表征变容管的射频寄生效应.提出了具体的参数提取方法,将测试的S参数导入到安捷伦IC-CAP建模软件提取参数,测试结构引入高频寄生采用(open+ short)去嵌方法进行去嵌.通过调节模型参数拟合测试曲线得到FinFET变容管模型.该模型可精确表述FinFET变容管全工作区域特性,解决传统MOS变容管模型无法准确描述三维FinFET器件变容特性的问题.模型和模型参数提取方法采用20个硅鳍、16个栅指、158 nm栅长、578 nm栅宽的FinFET变容管进行建模验证,模型仿真和测试所得C-V,R-V和S参数特性吻合良好.     

基于体硅衬底制作全耗尽FinFET器件的工艺方案

随着MOS器件缩小到纳米尺寸,为了改善器件性能,三维全耗尽FinFET器件受到广泛关注和研究.基于体硅衬底,已实现不同结构的FinFET,如双栅、三栅、环栅等结构.不同于SOI衬底FinFET,对于双栅或三栅结构,体硅衬底制作FinFET可能存在源漏穿通问题,对于环栅FinFET器件,工艺实现是一个很大的挑战.综述了目前解决源漏穿通问题的各种工艺方案,提出了全新的基于体硅衬底制作环栅FinFET的工艺方案,并展示了关键步骤的具体工艺实验结果.     

适用于按比例缩小至亚10nm的圆柱体全包围栅场效应管仿真

提出了一种适用于按比例缩小至亚10nm的圆柱体全包围栅场效应管.报道了圆柱体全包围栅场效应管器件物理分析、技术仿真结果以及器件制作详细工艺流程.与其他常规鳍形场效应管器件(FinFET)相比,该器件特别适用于解决常规鳍形场效应管器件所面临的问题,进一步提高器件性能及按比例缩小能力.技术仿真结果显示,圆柱体全包围栅场效应管具备许多常规鳍形场效应管器件,其中包括长方体全包围栅场效应管所不具备的优点.就圆柱体全包围栅场效应管器件结构而言,该器件由无数多个将圆柱体形沟道全部包围的栅所控制.由于克服了由不对称场的积聚,如锐角效应所导致的漏电,器件沟道的电完整性得到很大改善.详细讨论了器件制作工艺流程,提出的工艺流程简单并且与常规CMOS工艺流程兼容.     

适用于按比例缩小至亚10nm的圆柱体全包围栅场效应管仿真

提出了一种适用于按比例缩小至亚10nm的圆柱体全包围栅场效应管.报道了圆柱体全包围栅场效应管器件物理分析、技术仿真结果以及器件制作详细工艺流程.与其他常规鳍形场效应管器件(FinFET)相比,该器件特别适用于解决常规鳍形场效应管器件所面临的问题,进一步提高器件性能及按比例缩小能力.技术仿真结果显示,圆柱体全包围栅场效应管具备许多常规鳍形场效应管器件,其中包括长方体全包围栅场效应管所不具备的优点.就圆柱体全包围栅场效应管器件结构而言,该器件由无数多个将圆柱体形沟道全部包围的栅所控制.由于克服了由不对称场的积聚,如锐角效应所导致的漏电,器件沟道的电完整性得到很大改善.详细讨论了器件制作工艺流程,提出的工艺流程简单并且与常规CMOS工艺流程兼容.     

FinFET器件总剂量效应研究进展

全面综述鳍式场效应晶体管(FinFET)的总剂量效应,包括辐照期间外加偏置、器件的工艺参数、提高器件驱动能力的特殊工艺、源/漏掺杂类型以及不同栅介质材料和新沟道材料与FinFET总剂量效应的关系。对于小尺寸器件,绝缘体上硅(SOI)FinFET比体硅FinFET具有更强的抗总剂量能力,更适合于高性能抗辐照的集成电路设计。此外,一些新的栅介质材料和一些新的沟道材料的引入,如HfO₂和Ge,可以进一步提高FinFET器件的抗总剂量能力。     

一种新型高性能FinFET的设计与特性分析

针对CMOS器件随着技术节点的不断减小而产生的短沟道效应和漏电流较大等问题,设计了一种新型直肠形鳍式场效应晶体管(FinFET),并将该新型器件与传统的矩形结构和梯形结构的FinFET通过Sentaurus TCAD仿真软件进行对比。结果表明,当栅极长度控制在10 nm时,新型器件相比于另外两种传统的FinFET具有更小的鳍片尺寸,且鳍片高度不低于抑制短沟道效应的临界值。仿真结果显示,这种新型的FinFET具有更好的开关特性和亚阈值特性。同时,该器件在射频方面的特性参数也显示出该器件具有较高性能,并有一定的实际应用价值。     

新型低Cgs射频LDMOS器件设计

为了降低栅源寄生电容Cgs,提出了一种带有阶梯栅n埋层结构的新型射频LDMOS器件;采用Tsuprem4软件对其进行仿真分析,重点研究了n埋层掺杂剂量和第二阶梯栅氧厚度对栅源寄生电容Cgs的影响,并结合传统的射频LDMOS基本结构对其进行优化设计。结果表明：这种新型结构与传统的射频LDMOS器件结构相比,使得器件的栅源寄生电容最大值降低了15.8%,截止频率提高了7.6%,且器件的阈值电压和击穿电压可以维持不变。     

金属栅/高k基FinFET研究进展

对比传统的平面型晶体管,总结了三维立体结构FinFET器件的结构特性。结合MOS器件栅介质材料研究进展,分别从纯硅基、多晶硅/高k基以及金属栅/高k基三个阶段综述了Fin-FET器件的发展历程,分析了各阶段FinFET器件的材料特性及其在等比缩小时所面临的关键问题,并着重从延迟时间、可靠性和功耗三方面分析了金属栅/高k基FinFET应用于22 nm器件的性能优势。基于短沟道效应以及界面态对器件性能的影响,探讨了FinFET器件尺寸等比缩小可能产生的负面效应及其解决办法。分析了FinFET器件下一步可能的发展方向,主要为高迁移率沟道材料、立体型栅结构以及基于新原理的电子器件。     

绝缘体上硅FinFET亚阈值摆幅研究

在新型多栅器件栅电容模型的研究中,量子电容随着沟道长度及栅氧化层厚度的不断减小而变得越发不可忽略。推导了基于绝缘体上硅(SOI)工艺技术的鳍式场效应晶体管(FinFET)的量子电容,并通过构建囊括量子电容的内部电容网络模型推导了亚阈值摆幅。采用Matlab软件,仿真验证了量子电容对亚阈值摆幅的影响。提出了亚阈值摆幅的优化方法,为如何选取合适的器件尺寸来优化某个特定设计目标的性能提供了指导。     

一种基于非平衡态格林函数的准三维FinFET模型

提出了一种针对FinFET器件的准三维量子力学模型.采用非平衡态格林函数方法计算器件中的弹道输运电流,同时在器件垂直于沟道方向的横截面上求解二维的薛定谔方程来得到载流子的态密度分布,最终实现与三维泊松方程的自恰求解.模拟结果显示纳米尺度的FinFET器件具有良好的开关特性和亚阈值特性.这个模型还能适用于量子线等其他三维结构的纳米器件.     

基于25 nm FinFET结构的SRAM单粒子效应研究

对基于25 nm FinFET结构的SRAM单粒子效应进行研究。使用Synopsys Sentaurus TCAD仿真软件进行器件工艺校准,并对独立3D FinFET器件以及包含FinFET器件和HSpice模型的混合电路(如6管SRAM单元)进行单粒子瞬态仿真。通过改变重粒子入射条件,分析影响瞬态电流峰值、脉宽、漏极翻转阈值等参数的因素。研究发现,混合模型中,FinFET结构器件的漏极翻转阈值为0.023 MeV·cm²/mg,对未来基于FinFET结构的器件及电路结构的加固提出了更高的要求。     

Analysis of the Effects of Fringing Electric Field on FinFET Device Performance and Structural Optimization Using 3-D Simulation

In this paper, the potential impact of parasitic capacitance resulting from fringing field on FinFET device performance is studied in detail using a 3-D simulator implemented with quantum-mechanical models. It was found that fringing field from gate to source contributes significantly to FinFET performance and speed. The strength of fringing field is closely related to device features such as gate-dielectric thickness, the spacer width, fin width and pitch, as well as the gate height. For undoped fin with underlapping (nonoverlapping source/drain) gate, a thinner spacer with higher kappa value enhances the gate control of short-channel effects (SCEs) and reduces the source-to-drain leakage current. Our results also suggest that reducing the high- gate-dielectric thickness is no longer an effective approach to improve performance in small FinFET devices due to the strong fringing effect. However, the introduction of thin metal gate in a multifin device was found beneficial to device speed without compromising on current drive and SCE.     

Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETs

This paper analyzes the geometry-dependent parasitic components in multifin double-gate fin field-effect transistors (FinFETs). Parasitic fringing capacitance and overlap capacitance are physically modeled as functions of gate geometry parameters using a conformal mapping method. Also, a physical gate resistance model is presented, combined with parasitic capacitive couplings between source/drain fins and gates. The effects of geometrical parameters on FinFET design under different device configurations are thoroughly studied     

Quantum mechanical analytical modeling of nanoscale DG FinFET: evaluation of potential,threshold voltage and source/drain resistance

Two-dimensional (2D) quantum mechanical analytical modeling has been presented in order to evaluate the 2D potential profile within the active area of FinFET structure. Various potential profiles such as surface, back to front gate and source to drain potential have been presented in order to appreciate the usefulness of the device for circuit simulation purposes. As we move from source end of the gate to the drain end of the gate, there is substantial increase in the potential at any point in the channel. This is attributed to the increased value of longitudinal electric field at the drain end on application of a drain to source voltage. Further, in this paper, the detailed study of threshold voltage and its variation with the process parameters are presented. A threshold voltage roll-off with fin thickness is observed for both theoretical and experimental results. The fin thickness is varied from 10 nm to 60 nm. The percentage roll-off for our model is 77% and that for experimental result it is 75%. Form the analysis of source/drain (S/D) resistance, it is observed that for a fixed fin width, as the channel length increases, there is an enhancement in the parasitic S/D resistance. This can be inferred from the fact that as the channel length decreases, quantum confinement along the S/D direction becomes more extensive. For our proposed devices a close match is obtained with the results through the analytical model and reported experimental results, thereby validating our proposed QM analytical model for DG FinFET device.     

Study of fin tapering effect in nanoscale symmetric dual-k spacer (SDS) hybrid FinFETs

Symmetric Dual-k Spacer (SDS) Hybrid FinFETs is a novel device, which combines three significant technologies i.e., 2-D ultra-thin-body (UTB), 3-D FinFET, and symmetric spacer engineering on a single silicon on insulator (SOI) platform. For the first time, this article systematically analyzes the impacts of non-rectangular fin shape on various performance metrics of SDS Hybrid FinFETs. Under distinctive inclination fin angles as prescribed by the process technology, the performances of the device at different fin heights are examined. This work evaluates the response of fin tapering as well as fin height on parameters like threshold voltage (V_th), subthreshold slope (SS), on current (I_on), transconductance (g_m), transconductance generation factor (TGF), and total gate capacitance (C_gg) in SDS Hybrid FinFETs. Optimum structural configuration is thus proposed to fabricate the hybrid device in sub-20 nm FinFET architecture.     

FinFET器件的集约阈电压模型

对FinFET器件(或称三栅MOSFET器件)的二维截面做了解析静电学分析以得出阈电压的计算公式.结果显示,由于三栅结构在高度方向的限制作用,需要引入一个H系数来修正栅电容,随着高度不断变大,它渐近于双栅MOSFET器件的情况.由该解析模型得出的电势分布与数值模拟结果吻合.提出了一个包含量子效应的Fin-FET器件的集约阈电压模型,结果表明,当高度或者顶栅的氧化层厚度变小时,栅电容及阈电压都会上升,这与FinFET设计时发现的趋势是相符合的.     

Compact Threshold Voltage Model for FinFETs

A 2D analytical electrostatics analysis for the cross-section of a FinFET (or tri-gate MOSFET) is performed to calculate the threshold voltage.The analysis results in a modified gate capacitance with a coefficient Ｈ introduced to model the effect of trigates and its asymptotic behavior in 2D is that for double-gate MOSFET.The potential profile obtained analytically at the cross-section agrees well with numerical simulations.A compact threshold voltage model for FinFET,comprising quantum mechanical effects,is then proposed.It is concluded that both gate capacitance and threshold voltage will increase with a decreased height,or a decreased gate-oxide thickness of the top gate，which is a trend in FinFET design.     

Process and characteristics of modified Schottky barrier (MSB) p-channel FinFETs

A novel modified Schottky barrier p-channel FinFET (MSB FinFET) has been successfully demonstrated previously. In this paper, the detailed process conditions, especially the formation of MSB junctions, has been presented. Device characteristics as well as the geometry effect are also discussed extensively. In the MSB FinFETs fabricated by the two-step silicidation and implant-to-silicide techniques (ITS), an ultrashort and defect-free source/drain extension (SDE) could be formed at a temperature as low as 600/spl deg/C, resulting in excellent electrical characteristics. The ultrashort SDE could effectively thin out the SB width between source/channel during on-state or broaden and elevate it between drain/channel during off-state. A leakage mechanism of MSB FinFETs similar to the conventional ones was identified by the activation energy analysis. Strong fin width dependence of the electrical characteristics was also found in the proposed devices. When the fin width becomes larger than the silicide grain size, the multigrain structure results in a rough front edge of the MSB junction, which in turn degrades the short-channel device performance. This result indicates that the MSB device is suitable for use as FinFET. The low thermal budget of the MSB FinFET relaxes the thermal stability issue for metal gate/high-/spl kappa/ dielectric integration. It is considered that the proposed MSB FinFET is a very promising nanodevice.     

Improving bulk FinFET DC performance in comparison to SOI FinFET

The implementation of FinFET structure in bulk silicon wafers is very attractive due to low-cost technology and compatibility with standard bulk CMOS in comparison with silicon-on-insulator (SOI) FinFET. SOI and bulk FinFET were analyzed by a three-dimensional numerical device simulator. We have shown that bulk FinFET with source/drain-to-body (S/D) junctions shallower than gate-bottom has equal or better subthreshold performance than SOI FinFET. By reducing S/D junction depth, fin width scaling for suppression of short-channel-effects (SCEs) can be relaxed. On-state performance has also been examined and drain current difference between the SOI and bulk FinFET at higher body doping levels has been explained by investigating enhanced conduction in silicon-oxide interface corners. By keeping the body doping low and junctions shallower than the gate-bottom, bulk FinFET characteristics can be improved with no increase in process complexity and cost.