Probabilistic counter updates for predictor hysteresis and bias

Hardware predictor designers have incorporated hysteresis and/or bias to achieve desired behavior by increasing the number of bits per counter. Some resulting proposed predictor designs are currently impractical because their counter tables are too large. We describe a method for dramatically reducing the amount of storage required for a predictor's counter table with minimal impact on prediction accuracy. Probabilistic updates to counter state are implemented using a hardware pseudo-random number generator to increment or decrement counters a fraction of the time, meaning fewer counter bits are required. We demonstrate the effectiveness of probabilistic updates in the context of Fields et al.'s critical path predictor, which employs a biased 6-bit counter. Averaged across the SPEC CINT2000 benchmarks, our 2-bit and 3-bit probabilistic counters closely approximate a 6-bit deterministic one (achieving speedups of 7.75% and 7.91% compared to 7.94%) when used for criticality-based scheduling in a clustered machine. Performance degrades gracefully, enabling even a 1-bit probabilistic counter to outperform the best 3-bit deterministic counter we found.     

Reset: A Reconfigurable state encoding technique for FSM to achieve security and hardware optimality

Digital controllers are prone to side-channel and fault-insertion attacks that lead hardware security as the primary issue in its creation. On the other hand, optimal hardware design is also the prime concern while crafting a digital controller. A finite state machine (FSM) presents a novel framework for any complex digital controller, and a state assignment technique is used for its optimization. In this article, a reconfigurable state encoding technique (ReSET) is proposed for FSM to obtain security and hardware optimality. ReSET is a deterministic method, which employs algorithms such as, (a) robust quadratic sum code based state assignment, and (b) gradient-based interior point approach based state assignment. A user-defined reconfiguration factor is introduced in ReSET by which the degree of security and hardware optimality is configured for the FSM. An extensive set of experiments are executed to validate the ReSET’s feasibility, which also proves ReSET’s superiority in terms of area, computation time, power, and error masking probabilities over the state-of-art literature. To the best of author’s knowledge, ReSET has made the first successful attempt to achieve security as well as hardware optimality for an FSM by setting the reconfiguration factor.     

基于原子混淆的通用侧信道漏洞修补方法

包含侧信道漏洞的代码在程序被执行时会表现出与输入有关的非功能性行为,攻击者利用微架构的侧信道攻击可获取这些行为,并通过分析行为与输入之间的关联模式恢复应用数据内容,达到窃取用户机密数据的目的.软件层的侧信道漏洞修补方法带给程序的性能损耗较低,并且因为无须修改硬件或系统,可实现快速修补和大范围部署,成为密码算法实现采用的...     

后量子加密算法的硬件实现综述

现有的密码体制大多基于RSA、ECC等公钥密码体制,在信息安全系统中实现密钥交换、数字签名和身份认证等,有其独特的优势,其安全性分别依赖于解决整数分解问题和离散对数问题的难度。近年来,随着量子计算机的快速发展,破解上述数学问题的时间大幅减少,这将严重损害数字通信的安全性、保密性和完整性。与此同时,一个新的密码学领域,即后量子密码学应运而生,基于它的加密算法可以对抗量子计算机的攻击,因此成为近年来的热点研究方向。2016年以来,NIST向世界各地的研究者征集候选抗量子密码学方案,并对全部方案进行安全性、成本和性能的评估,最终通过评估的候选方案将被标准化。本文比较了NIST后量子密码学算法征集(第2轮、第3轮)的各个方案,概述目前后量子加密算法的主要实现方法:基于哈希、基于编码、基于格和基于多变量,分析了各自的安全性,签名参数及计算量的特点以及后期的优化方向。PQC算法在硬件实现上的挑战其一是算法规范的数学复杂性,这些规范通常是由密码学家编写的,关注的重点是其安全性而非实现的效率,其二需要存储大型公钥、私钥和内部状态,这可能会导致不能实现真正的轻量级,从而降低硬件实现的效率。本文重点介绍了目前后量子加密算法的硬件实现方式,包括PQC硬件应用程序编程接口的开发,基于HLS的抽象实现和基于FPGA/ASIC平台的硬件实现。PQC方案的硬件化过程中不仅需要算法的高效实现,同时需要抵抗针对硬件结构的侧信道攻击。侧信道攻击可以通过来自目标设备泄露的相关信息来提取密码设备的密钥。本文讨论了后量子加密算法在具体实现和应用中受到侧信道攻击类别和防御对策。     

一种针对分组密码S盒的组合侧信道攻击方法*

近年来随着半导体工艺的飞速发展和信息安全的重要性不断增强,越来越多的硬件嵌入了密码算法以保证数据安全性。针对嵌入了FPGA密码芯片的设备在运行算法时泄漏的侧信道信息进行了研究,提出一种改进分组密码S盒的组合侧信道攻击方案,该方案由差分功耗攻击、模板攻击、和毛刺攻击构成。通过传统的差分功耗攻击确定S盒运行的时间区间,然后针对目标S盒的输入输出利用一个时钟周期内逻辑门毛刺个数与部分功耗线性相关的方法,采用线性模型匹配算法恢复密钥并减少了基于多元高斯模型匹配的计算量,为今后提高侧信道攻击的效率提供依据。     

基于改进蚁群算法的防护策略选择模型

网络攻击的多步性增加了预测攻击路径的难度,难以对攻击提供有效的安全防护,而传统的解决方案需要花费较高的成本来修复大量的网络漏洞。针对上述问题,对网络攻击的防护问题展开研究,提出一种基于改进蚁群算法的防护策略选择模型（Hardening Measures Selection Mode based on an Improved Ant?Colony?Optimization,HMSMIACO）。该模型由三部分组成：在现有攻击图的基础上,运用能够描述多步原子攻击间因果关系的贝叶斯信念网络构建用于评估网络安全风险的概率攻击图;结合防护成本与收益的量化指标,提出一种能够模拟攻击者决策过程的路径预测算法;鉴于防护策略选择问题是一个NP-hard问题,选择适用于中等规模网络环境的一种改进蚁群算法求解该问题,并获得该网络环境下近似最优的防护策略集。最后,通过实验说明了HMSMIACO在降低网络安全风险问题上的可行性与有效性。     

安全漏洞的统一描述研究

安全漏洞统一格式描述可以使不同的安全产品从同一描述进行漏洞信息的更新，减少了不同安全产品公司各自维护漏洞库的投入，达到了不同厂家安全产品漏洞信息的同步与数据描述的一致。本文叙述了利用XML进行安全漏洞统一格式描述的GVML实现及其在安全产品中的应用。     

后量子密码算法的侧信道攻击与防御综述

为解决量子计算对公钥密码安全的威胁,后量子密码成为密码领域的前沿焦点研究问题.后量子密码通过数学理论保证了算法安全性,但在具体实现和应用中易受侧信道攻击,这严重威胁到后量子密码的安全性.本文基于美国NIST第二轮候选算法和中国CACR公钥密码竞赛第二轮的候选算法,针对基于格、基于编码、基于哈希、基于多变量等多种后量子密码算法进行分类调研,分析其抗侧信道攻击的安全性现状和现有防护策略.为了深入分析后量子密码的侧信道攻击方法,按照算法核心算子和攻击类型进行分类,总结了针对各类后量子密码常用的攻击手段、攻击点及攻击评价指标.进一步,根据攻击类型和攻击点,梳理了现有防护策略及相应的开销代价.最后我们在总结部分,根据攻击方法、防护手段和防护代价提出了一些安全建议,并且还分析了未来潜在的侧信道攻击手段与防御方案.     

A Secure Hardware Implementation for Elliptic Curve Digital Signature Algorithm

Since the end of the 1990s, cryptosystems implemented on smart cards have had to deal with two main categories of attacks: side-channel attacks and fault injection attacks. Countermeasures have been developed and validated against these two types of attacks, taking into account a well-defined attacker model. This work focuses on small vulnerabilities and countermeasures related to the Elliptic Curve Digital Signature Algorithm (ECDSA) algorithm. The work done in this paper focuses on protecting the ECDSA algorithm against fault-injection attacks. More precisely, we are interested in the countermeasures of scalar multiplication in the body of the elliptic curves to protect against attacks concerning only a few bits of secret may be sufficient to recover the private key. ECDSA can be implemented in different ways, in software or via dedicated hardware or a mix of both. Many different architectures are therefore possible to implement an ECDSA-based system. For this reason, this work focuses mainly on the hardware implementation of the digital signature ECDSA. In addition, the proposed ECDSA architecture with and without fault detection for the scalar multiplication have been implemented on Xilinx field programmable gate arrays (FPGA) platform (Virtex-5). Our implementation results have been compared and discussed. Our area, frequency, area overhead and frequency degradation have been compared and it is shown that the proposed architecture of ECDSA with fault detection for the scalar multiplication allows a trade-off between the hardware overhead and the security of the ECDSA.     

适于软硬件实现的安全轻量S盒的设计

随着物联网的发展,轻量级分组密码算法的设计显得尤为重要。S盒是对称密码算法的关键部件。许多加密算法的硬件实现过程易受侧信道攻击,门限实现是一种基于秘密共享和多方计算的侧信道攻击对策。通过简单地对三次布尔函数中的变量进行循环移位,构建密码性质最优的4×4安全轻量S盒,并且为所构造的S盒设计了门限实现方案来抵御侧信道攻击,该方案是可证安全的。该方法构造的S盒的四个分量函数的实现电路相同,极大地降低了硬件实现的复杂度。给定S盒的一个分量,其余的三个分量可通过该分量的循环移位获得,这样大大降低硬件实现成本,易于快速软件实现。     

同时多线程处理器上的动态分支预测器设计方案研究

同时多线程处理器（SMT）每个周期能够从多个线程中发射指令执行，从而大大地提高了超标量微处理器的指令吞吐量，但多个线程的同时执行也带来了许多硬件资源的共享冲突问题.其中，多个线程共享分支预测硬件的方案会对分支预测精度产生较大的影响.研究SMT处理器中分支处理方案对于处理器整体性能的影响，对于指导SMT处理器的设计是十分重要的.本文利用SMT处理器模拟器，针对各线程运行独立应用的SMT结构实验评估了几种著名的分支预测方案;给出了在单线程和多线程情况下，分支预测方案对分支预测精度和处理器整体性能的影响的分析;总结出在这样的SMT结构中，各线程拥有独立的预测器是一种较好的选择，并且由于各独立预测器可以采用小而简单的结构，所以不会带来太多的硬件开销.     

Side-channel attacks and learning-vector quantization

The security of cryptographic systems is a major concern for cryptosystem designers, even though cryptography algorithms have been improved. Side-channel attacks, by taking advantage of physical vulnerabilities of cryptosystems, aim to gain secret information. Several approaches have been proposed to analyze side-channel information, among which machine learning is known as a promising method. Machine learning in terms of neural networks learns the signature (power consumption and electromagnetic emission) of an instruction, and then recognizes it automatically. In this paper, a novel experimental investigation was conducted on field-programmable gate array (FPGA) implementation of elliptic curve cryptography (ECC), to explore the efficiency of side-channel information characterization based on a learning vector quantization (LVQ) neural network. The main characteristics of LVQ as a multi-class classifier are that it has the ability to learn complex non-linear input-output relationships, use sequential training procedures, and adapt to the data. Experimental results show the performance of multi-class classification based on LVQ as a powerful and promising approach of side-channel data characterization.     

A Secure IoT Firmware Update Scheme Against SCPA and DoS Attacks

In the IEEE S&P 2017,Ronen et al.exploited side-channel power analysis (SCPA) and approximately 5000 power traces to recover the global AES-CCM key that Philip Hue lamps use to decrypt and authenticate new firmware.Based on the recovered key,the attacker could create a malicious firmware update and load it to Philip Hue lamps to cause Internet of Things (IoT) security issues.Inspired by the work of Ronen et al.,we propose an AES-CCM-based firmware update scheme against SCPA and denial of service (DoS) attacks.The proposed scheme applied in IoT terminal devices includes two aspects of design (i.e.,bootloader and application layer).Firstly,in the bootloader,the number of updates per unit time is limited to prevent the attacker from acquiring a sufficient number of useful traces in a short time,which can effectively counter an SCPA attack.Secondly,in the application layer,using the proposed handshake protocol,the IoT device can access the IoT server to regain update permission,which can defend against DoS attacks.Moreover,on the STM32F405+M25P40 hardware platform,we implement Philips' and the proposed modified schemes.Experimental results show that compared with the firmware update scheme of Philips Hue smart lamps,the proposed scheme additionally requires only 2.35 KB of Flash memory and a maximum of 0.32 s update time to effectively enhance the security of the AES-CCM-based firmware update process.     

用于硬件木马检测的电磁辐射分析方法研究

随着集成电路产业全球化的发展，硬件木马已成为集成电路的主要安全威胁之一。目前能较好权衡检测成本与检测能力的侧信道分析方法越来越受到研究人员的关注，其中，电磁辐射分析方法是研究热点之一。重点分析并验证电磁辐射分析方法对硬件木马的检测能力，并探究限制其检测性能的原因。在现场可编程逻辑门阵列（FPGA）上进行验证实验，实验结果表明，电磁辐射分析方法可以很好地检测电磁辐射频率分布独特的硬件木马电路，但无法适用于电磁辐射频率分布复杂的硬件木马。     

Security beyond cybersecurity: side-channel attacks against non-cyber systems and their countermeasures

Side-channels are unintended pathways within target systems that leak internal information, exploitable via side-channel attack techniques that extract the target information, compromising the system’s security and privacy. Side-channel attacks are well established within the cybersecurity domain, and thus their cyber-physical systems are actively defended with countermeasures. Non-cyber systems are equally as vulnerable to side-channel attacks; however, this is largely unrecognised and therefore countermeasures to defend them are limited. This paper surveys side-channel attacks against non-cyber systems and investigates the consequent security and privacy ramifications. Side-channel attack techniques rely on respective side-channel properties in order to succeed; therefore, countermeasures that disrupt each side-channel property are identified, effectively thwarting the side-channel attack. This principle is captured within a countermeasure algorithm: a systematic and extensible approach to identifying candidate countermeasures for non-cyber systems. We validate the output of this process by showing how the candidate countermeasures could be applied in the context of each non-cyber system and in the real world. This work provides an extensible platform for translating cybersecurity-derived side-channel attack research into defending systems from non-cyber domains.

     

Winter is here! A decade of cache-based side-channel attacks,detection & mitigation for RSA

Timing-based side-channels play an important role in exposing the state of a process execution on underlying hardware by revealing information about timing and access patterns. Side-channel attacks (SCAs) are powerful cryptanalysis techniques that focus on the underlying implementation of cryptographic ciphers during execution rather than attacking the structure of cryptographic functions. This paper reviews cache-based software side-channel attacks, mitigation and detection techniques that target various cryptosystems, particularly RSA, proposed over the last decade (2007–2018). It provides a detailed taxonomy of attacks on RSA cryptosystems and discusses their strengths and weaknesses while attacking different algorithmic implementations of RSA. A threat model is presented based on the cache features that are being leveraged for such attacks across cache hierarchy in computing architectures. The paper also provides a classification of these attacks based on the source of information leakage. It then undertakes a qualitative analysis of secret key retrieval efficiency, complexity, and the features being exploited on target cryptosystems in these attacks. The paper also discusses the mitigation and detection techniques proposed against such attacks and classifies them based on their effectiveness at various levels in caching hardware and leveraged features. Finally, the paper discusses recent trends in attacks, the challenges involved in their mitigation, and future research directions needed to deal with side-channel information leakage.     

基于存储网关的数据安全去重方案

在实行客户端去重的云存储系统中,通过所有权证明可以解决攻击者仅凭借文件摘要获得整个文件的问题。然而,基于所有权证明的去重方案容易遭受侧信道攻击。攻击者通过上传文件来观察是否发生去重,即可判断该文件是否存在于云服务器中。基于存储网关提出一种改进的所有权证明去重方案,存储网关代替用户与云服务器进行交互,使得去重过程对用户透明,并采用流量混淆的方法抵抗侧信道攻击和关联文件攻击。分析与比较表明,该方案降低了客户端计算开销,并提高了安全性。     

基于Chebyshev的概率公钥密码体制

介绍了Chebyshev多项式的定义和相关性质, 针对确定性Chebyshev多项式公钥密码体制进行了研究, 发现其不能抵抗选择密文攻击。结合抵抗选择密文攻击的安全模型, 提出了基于有限域的Chebyshev多项式的概率公钥密码体制, 分析结果表明该密码体制是正确的。通过归约证明, 该密码体制能够抵挡适应性选择密文攻击, 具有抵抗选择密文攻击的IND-CCA2安全性。     

Generating optimized gate level information flow tracking logic for enforcing multilevel security

Vulnerabilities such as design flaws, malicious codes and covert channels residing in hardware design are known to expose hard-to-detect security holes. However, security hole detection methods based on functional testing and verification cannot guarantee test coverage or identify malicious code triggered under specific conditions and hardware-specific covert channels. As a complement approach to cipher algorithms and access control, information flow analysis techniques have been proved to be effective in detecting security vulnerabilities and preventing attacks through side channels. Recently, gate level information flow tracking (GLIFT) has been proposed to enforce bittight information flow security from the level of Boolean gates, which allows detection of hardware-specific security vulnerabilities. However, the inherent high complexity of GLIFT logic causes significant overheads in verification time for static analysis or area and performance for physical implementation, especially under multilevel security lattices. This paper proposes to reduce the complexity of GLIFT logic through state encoding and logic optimization techniques. Experimental results show that our methods can reduce the complexity of GLIFT logic significantly, which will allow the application of GLIFT for proving multilevel information flow security.     

基于线性函数的值预测器设计

在微处理器中,为突破数据流限制以获取更高的指令级并行,指令值预测研究日益得到广泛重视,多种值预测器设计方案被提出。这些预测器可以获得很高的性能,但在性价比优化设计上还有很大的研究空间。本文提出的基于线性函数的值预测器在性能和硬件耗费两方面实现了较好的折衷。SPEC CINT95基准测试程序集模拟结果表明,与复杂的基于stride和2level的混和值预测器相比,基于线性函数的值预测器在性能上仅有很小损失。