一种电场调制载流子存储槽栅双极型晶体管

提出了一种性能优良的电场调制载流子存储槽栅双极型晶体管(CSTBT)。结合电场调制原理,在器件的载流子存储(CS)层引入P掺杂条,改善器件栅极下方氧化硅拐角处的电场分布,防止器件提前发生雪崩击穿,提高了器件的击穿电压。器件处于关断状态时,内部大量的空穴载流子通过CS层中未完全耗尽的P掺杂条到达发射极,抑制了CS层阻挡空穴的作用,有效提高了器件的关断速度。与传统CSTBT器件相比,改进器件的击穿电压值提高了379 V,关断时间缩短了19.1%,器件性能大幅提高。     

具有抑制边缘击穿的层叠结结构的平面型InGaAs/InP盖革雪崩光电二极管的设计

通过有限元分析设计了具有抑制边缘击穿的层叠边缘结结构的平面型InGaAs/InP盖革雪崩光电二极管. 通过仔细地控制中央区域结的深度,光电二极管的击穿电压降至54.3V; 同时通过调整InP倍增层的掺杂浓度和厚度,沿器件中轴的电场分布也得到了控制. 在有源区的边缘采用层叠pn结结构有效地抑制了过早边缘击穿现象. 仿真模拟显示四层层叠结构是边缘击穿抑制效果和制造工艺复杂度的一个好的折衷方案,该结构中峰值电场强度为5.2E5kV/cm,空穴离化积分最大值为1.201. 本文提供了一种设计高性能的InGaAs/InP光子计数雪崩光电二极管的有效方法.     

硅基雪崩光电探测器倍增层掺杂的研究

硅基雪崩光电探测器的器件性能与倍增层的掺杂浓度有着密切联系。研究了硅基雪崩光电探测器倍增层的掺杂浓度对雪崩击穿电压和光谱响应度等特性的影响。在硼的注入剂量由5.0×1012 cm-2减小为2.5×1012cm-2时,倍增层内电场强度逐渐降低,吸收区电场强度迅速增大,器件的雪崩击穿电压由16.3V迅速上升到203V,而光谱响应在95%的击穿电压下,峰值响应波长由480nm红移至800nm,对应的响应度由11.2A/W剧增到372.3A/W。综合考虑光谱响应和雪崩击穿电压的影响,在硼注入剂量为3.5×1012 cm-2时,可获得击穿电压为43.5V和响应度为342.5A/W的器件模型,对实际器件的制备具有一定参考价值。     

具有抑制边缘击穿的层叠结结构的平面型InGaAs/InP盖革雪崩光电二极管的设计

通过有限元分析设计了具有抑制边缘击穿的层叠边缘结结构的平面型InGaAs/InP盖革雪崩光电二极管.通过仔细地控制中央区域结的深度,光电二极管的击穿电压降至54.3V;同时通过调整InP倍增层的掺杂浓度和厚度,沿器件中轴的电场分布也得到了控制.在有源区的边缘采用层叠pn结结构有效地抑制了过早边缘击穿现象.仿真模拟显示四层层叠结构是边缘击穿抑制效果和制造工艺复杂度的一个好的折衷方案,该结构中峰值电场强度为5.2×105kV/cm,空穴离化积分最大值为1.201.本文提供了一种设计高性能的InGaAs/InP光子汁数雪崩光电二极管的有效方法.     

6.5 kV SiC光控晶闸管的研制

基于Sentaurus TCAD软件,研制了一款6.5 kV SiC光控晶闸管.通过优化雪崩击穿模型,对多层外延材料的规格及渐变终端技术进行研究,有效抑制了芯片表面峰值电场,实现了6.5 kV的耐压设计;此外结合实际应用需求,对器件的开通特性进行了仿真模拟.在4英寸(1英寸=2.54 cm)SiC工艺平台制备了6.5 kV SiC光控晶闸管,并对器件性能进行了测试.测试结果显示,芯片击穿电压超过6.5 kV,在4 kV电源电压以及365 nm波长紫外光触发的条件下,器件导通延迟约为200 ns,脉冲峰值电流约为2.1 kA,最大导通电流变化率(di/dt)达到6.3 kA/μs,测试结果与仿真模拟结果基本一致.     

6H-SiC单极功率器件性能的温度关系

基于碳化硅材料电离系数和迁移率的温度依赖性,利用有效电离系数的Fulop近似,推出了6H-SiC单极性功率器件击穿电压和比导通电阻的温度依赖性解析表达式.理论预言的击穿电压和临界电场与先前的实验结果基本一致(误差小于10%),验证了理论模型的适用性.     

LDD功率器件表面电场解析模型及优化

提出低掺杂漏(Lightly Doped Drain,LDD)功率器件表面电场和电势解析模型。基于分区求解二维Poisson方程,获得二维表面电场和电势的解析表达式。借助此模型,研究器件结构参数对表面电场和电势的影响;计算漂移区长度与击穿电压的关系,分析了击穿电压随低掺杂漏区掺杂浓度和漂移区厚度的变化,从理论上揭示了获得最大击穿电压的条件。解析结果与数值结果吻合较好,验证了模型的准确性,该模型可用于硅基LDD功率器件的设计优化。     

表面注入D-RESURF器件耐压模型

建立表面注入双重降低表面电场(D-RESURF)结构击穿电压模型。D-RESURF器件在衬底纵向电场和Pb区附加电场的影响下,漂移区电荷共享效应增强,优化漂移区掺杂浓度增大,器件导通电阻降低。分析漂移区浓度和厚度对击穿电压的影响,获得改善击穿电压和导通电阻折中关系的途径。在满足最优表面电场和完全耗尽条件下,导出吻合较好的二维RESURF判据。在理论的指导下,成功研制出900 V的D-RESURF高压器件。     

GAT实现高电流增益与高雪崩击穿电压兼容特性分析

通过作者最近建立的关于电力半导体器件 GAT的集电结耗尽层电位分析和电场分布的二维解析模型定量研究了 GAT的雪崩击穿特性 ,并且定量解释了该器件实现高击穿电压与高电流增益兼容的实验结果。     

基于0.35μm CMOS工艺的APD器件仿真分析

提出了一种基于0.35μm CMOS工艺的、具有p+/n阱二极管结构的雪崩光电二极管(APD),器件引入了p阱保护环结构.采用silvaco软件对CMOS-APD器件的关键性能指标进行了仿真分析.仿真结果表明:p阱保护环的应用,明显降低了击穿电压下pn结边缘电场强度,避免了器件的提前击穿.CMOS APD器件的击穿电压为9.2V,工作电压下响应率为0.65 A/W,最大内部量子效率达到90％以上,响应速度能够达到6.3 GHz,在400～900 nm波长范围内,能够得到很大的响应度.     

Low dark current GaN avalanche photodiodes

We report the fabrication and characterization of GaN avalanche photodiodes grown on sapphire by metalorganic chemical vapor deposition. Current-voltage characteristics indicate a gain higher than 23. The photoresponse is independent of the bias voltage prior to the onset of avalanche gain which occurs at an electric field of ~4 MV/cm. Near avalanche breakdown, the dark current of a 30-μm diameter device is less than 100 pA. The breakdown shows a positive temperature coefficient of 0.03 V/K that is characteristic of avalanche breakdown     

Dynamic avalanche in diodes with local lifetime control by means of palladium

The increase of the static breakdown voltage and the reduction of dynamic avalanche in a fast recovery 2.5 kV/150 A P-i-N diode subjected to the radiation enhanced diffusion of a palladium are discussed. The in-diffusing palladium compensates the doping profile in a lightly doped N-base close to the anode junction. Using a device simulation, the increase of the breakdown voltage and the reduction of the dynamic avalanche are explained by the reduction of peak electric field in the additional low-doped P-type layer created by the compensation effect. This is presented for both a dc and transient device operation and confirmed experimentally as well. An improved technology curve for the static versus recovery losses at a high line voltage has been obtained. A high thermal budget of deep levels and a low leakage current are additional benefits of the method.     

Influence of surface texture on the defect‐induced breakdown behavior of multicrystalline silicon solar cells

The defect‐induced diode breakdown behavior in multicrystalline silicon solar cells, which is located at recombination active crystal defects, is influenced by the surface texturization because the wet chemical treatment selectively etches grain boundaries and dislocations, resulting in etch pits. On textured surfaces, the defect‐induced breakdown voltage is decreased, and the slope of the local reverse I–V characteristics in breakdown is steeper. We find that the local defect‐induced breakdown voltage correlates with the depth of the etch pits. It is suggested that the enhanced electric field in the space charge region at the tip could be superimposed by an electric field around metallic precipitates because of the internal Schottky contact formation with the surrounding silicon. The combined electric field could be responsible for the dependence of the defect‐induced breakdown behavior on the surface texture. Copyright © 2012 John Wiley & Sons, Ltd.     

薄硅层阶梯埋氧PSOI高压器件新结构

基于介质电场增强ENDIF理论,提出了一种薄硅层阶梯埋氧型部分SOI(SBPSOI)高压器件结构。埋氧层阶梯处所引入的电荷不仅增强了埋层介质电场,而且对有源层中的电场进行调制,使电场优化分布,两者均提高器件的击穿电压。详细分析器件耐压与相关结构参数的关系,在埋氧层为2μm,耐压层为0.5μm时,其埋氧层电场提高到常规结构的1.5倍,击穿电压提高53.5%。同时,由于源极下硅窗口缓解SOI器件自热效应,使得在栅电压15V,漏电压30V时器件表面最高温度较常规SOI降低了34.76K。     

Switching processes and dielectric breakdown in polycrystalline Nb2O5 films

Repetitive resistive switching from the high-to the low-resistance state in thin polycrystalline Nb₂O₅ films was investigated. The switching process, and dielectric breakdown, are associated with four successive conduction states. The thermal activation energy in the first conduction state is 0.35 eV and in the second state is 0.047 eV; in the third and fourth resistance states the temperature coefficient of resistance exhibits metallic behavior. The I-V relationship changes from the Poole-Frenkel mechanism in the first state to space-charge-limited conduction in the second state and a linear relation in the third and fourth states. These and other results indicate that dielectric breakdown occurs through a process of a metallic precipitation increasing in each consecutive state and the formation of a highly conductive filament in the fourth and final state in the dielectric breakdown process. The values of important switching parameters such as the threshold field for switching E_s, holding current and voltage I_h and V_h, switching time τ_s, delay time τ_d and recovery time τ_r are presented. The dependence of the delay time τ_d on the applied voltage and temperature is studied and the relation τ_d∝exp(−k(V/V_s)) is established, with k showing only a slight temperature dependence. Supported by the Office of Naval Research     

用于光子计数的InGaAs/InP SPAD设计

重点研究了InGaAs/InP SPAD的隧道贯穿电场、雪崩击穿电场、雪崩宽度与过偏电压的关系,提出了过偏电压的计算方法.分析了InGaAs/InP SPAD的基本特性即探测效率、暗计数率与其过偏电压、工作温度、量子效率、电场分布的依赖关系,提出了一种单光子InGaAs雪崩二极管的设计方法.设计制作了InGaAs/InP SPAD,并在门控淬灭模式下进行了单光子探测实验.结果表明:对于200m的SPAD,在过偏2 V、温度-40 ℃条件下,探测效率(PDE) 20%(1 550 nm)、暗计数率(DCR)20 kHz;对于50m的SPAD,在过偏2.5 V、温度-40 ℃条件下,探测效率(PDE) 23%(1 550 nm)、暗计数率(DCR)2 kHz.最后对实验结果进行了分析和讨论.     

The anomalous avalanche breakdown

Normally, the breakdown voltage of a p-n junction decreases with increasing doping density. But there are also cases in which the breakdown voltage increases with increasing doping density, e.g., for InSb in the doping range from 10¹³cm^-3to 2 × 10¹⁴cm^-3. The reason for the anomalous behavior is the saturation of the ionization coefficient with increasing electric field strength. The anomalous behavior can only be observed if the tunnel breakdown requires a higher field strength as the one required for saturation of the ionization coefficient. This paper presents a rather simple theory yielding analytical solutions for the normal and anomalous avalanche breakdown. Treated is the influence of the doping profile upon the breakdown voltage in plane junctions and the influence of the radius of curvature for cylindrical one-sided abrupt junctions. The influence of the temperature upon the breakdown voltage and the multiplication factor as function of voltage is calculated for one-sided abrupt plane junctions. Finally, the temperature and doping range for the anomalous avalanche breakdown and the transition region is plotted for the semiconductors InSb, InAs, CdHgTe, PbSnTe, Ge, Si, GaAs, and GaP.     

Mechanisms of temperature dependence of threshold voltage in high-k/metal gate transistors with different TiN thicknesses

The change in temperature coefficient of the threshold voltage (=dV_th/dT) for poly-Si/TiN/high-k gate insulator metal–oxide–semiconductor field-effect transistors (MOSFETs) was systematically investigated with respect to various TiN thicknesses for both n- and p-channel MOSFETs. With increasing TiN thickness, dV_th/dT shifts towards negative values for both n- and p-MOSFETs. A mechanism that changes dV_th/dT, depending on TiN thickness is proposed. The main origins are the work function of TiN (Φ_TiN) and its temperature coefficient (dΦ_TiN/dT). These are revealed to change when decreasing the thickness of the TiN layer, because the crystallinity of the TiN layer is degraded for thinner films, which was confirmed by ultraviolet photoelectron spectroscopy (UPS), transmission electron microscopy (TEM) and X-ray diffraction (XRD).