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随着微电子技术的发展,集成电路的芯片面积、集成度愈来愈大。芯片面积及集成度的增大带来了两个问题:一是成品率问题,二是可靠性问题。本文阐述了容错设计在实时信号处理用VLSI中的必要性、意义和研究内容;讨论了二维脉动阵列的容错并给出了算法;讨论了VLSI单元的完全自检查问题,并给出了实现电路;给出了VLSI的成品率与可靠性分析模型;最后分析了模拟结果并给出了结论。 相似文献
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提出一种面向容错的对地观测卫星任务调度模型,该模型采用主版本/副版本技术可以实现对任意时刻一颗卫星失效时的容错.在容错调度模型的基础上,提出了一种卫星容错调度算法FTSS.FTSS采用重叠技术,有效提高了卫星资源利用率.此外,FTSS采用了任务合成策略可以有效减少实际执行任务的个数从而进一步提高系统的可调度性.为了验证FTSS算法的性能,本文通过模拟实验对FTSS与其它3个基准算法进行了比较分析.实验结果表明FTSS优于其它算法,适合卫星实时任务容错调度. 相似文献
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IC优化设计及其成品率预测 总被引:3,自引:3,他引:0
IC成品率是与电路性能和制造成本及制造效益紧密相关的一个重要因素,在进行IC优化设计时,可将成品率与制造效益作为协调各性能指标的优化目标.针对这一问题,本文完善了IC成品率效益协调优化设计模型,提出了一种实现该模型的IC优化设计和成品率预测方法,并利用OrCAD/PSpice中的统计分析和电路性能分析的功能和特点,建立了相应的算法.实例表明,该方法及其实现算法是有效的. 相似文献
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随着芯片集成度的不断提高,芯片制造工艺进入深亚微米级以后,片上将会出现更多难以预测与消除的故障类型。为了实现可靠的片上通信,应用容错机制与算法是一个重要的解决方案。本文提出一种面向应用的NoC容错路由算法,该算法在重负载时使用带有部分故障的链路并使流量在网络中均匀分布。同时给出了实现该算法需要的扩展后的路由器结构。仿真结果表明,所提出的路由算法与现有的路由算法相比,具有更好的时延性能。 相似文献
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针对有向双环网络G(N;h)的容错问题,研究了有向双环网络G(N;h)容错节点所对应的等价节点的分布规律,给出一种有向双环网络G(N;h)的容错路由算法. 给出了当有向双环网络任意两个节点之间的最短路径出现故障时,找出另一条最短路径的方法. 此算法的时间复杂度为O(d). 相似文献
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低冗余并行总线容错技术 总被引:1,自引:1,他引:0
本文将从分析Multibus总线功能入后,讨论多种总线容错技术及实时重构总线系统的方法,并具体分析各种容错技术对可靠性指标的影响程度。 相似文献
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While designing fault tolerant systems using dynamic reconfiguration, choice regarding the size of the granule influences the area, the power and the delay overheads. In this paper, attempt has been made to determine the optimum granule size that would incur minimum overhead vis-à-vis other design parameters such as the number of faults to be tolerated etc. In order to facilitate the design process, mathematical expressions have been provided showing the relationships among the area of single granule, the number of the external connections, the area of the reconfiguration multiplexers and the probability of failure of the system. Optimum granule-sizes in designing various fault tolerant circuits from ripple carry adder to CORDIC as well as Viterbi decoder have been derived. 相似文献
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外部集中控制的可重构硬件容错系统,其重构控制算法复杂、重构时间开销大,且存在单点失效问题.本文研究芯片级分布式在线自主容错技术,提出了能够实现芯片级自修复的新型可重构硬件细胞阵列结构,阐述了互连资源的在线故障定位和自主修复方法.设计了功能细胞电路和容错开关块电路,采用分段定位法检测互连资源中多路器故障和连线开路故障,通过重配置布线和线移位操作分别实现多路器与连线故障自修复.以4位串并乘法器电路为例进行实验验证,分析了容错设计的硬件开销与时间开销,实验结果表明新方案的容错时间短、资源利用率高. 相似文献
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Lin H. Lombardi F. Lu M. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1993,1(1):76-79
The reconfiguration of multipipeline arrays in the presence of both faulty processing elements (PEs) and switching elements (SEs) is addressed. Different fault models are used for the PEs and SEs: a PE can be either fault free or faulty; a SE is modeled using a novel functional approach which relates its switching capabilities to its status. This permits a PE to retain a partial functionality in the presence of a fault. An appropriate transformation of the multipipeline array reconfiguration problem to a maximum flow problem is then presented. The conditions under which this transformation is possible, are fully analyzed. A reconfiguration algorithm based on the maximum flow algorithm is presented; the proposed algorithm is optimal as the number of reconfigured pipelines is maximized 相似文献
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This paper describes the design of a high performance Si-Gate CMOS LSI circuit for an Adaptive Delta Modulation System (ADM). The circuit design is based on 4 μ design rules. The size of the die is approximately 25 mm2 and the circuit operates synchronously under the control of an 8 MHz two phase non-overlapping clock. A fault tolerant scheme is used at the comparator section for reliability improvement purposes. The adaptation logic of the system is based on the algorithm introduced in [2] where a rigorous proof is provided for showing the optimality of the algorithm in terms of performance. This paper demonstrates the feasibility of implementing this algorithm with a single chip adaptive delta modulator. 相似文献
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随着芯片面积的增加及电路复杂性的增强,芯片的成品率逐渐下降,为了保证合理的成品率,人们将容错技术结合入了集成电路。文中首先概述了缺陷及其分布,然后概述了容错技术,并详细地叙述了动态容错技术中的两个关键问题:故障诊断及冗余单元的分配问题。 相似文献
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A large-scale asynchronous transfer mode (ATM) switch fabric that can be constructed with currently feasible technology is proposed. Based on analysis of the technology, it is found that module interconnection becomes the bottleneck for a large fast packet switch. Fault tolerance for the switch is achieved by dynamic reconfiguration of the module interconnection network. The design improves system reliability with relatively low hardware overhead. An abstract model of the replacement problem for the design is presented, and the problem is transformed into a well-known assignment problem. The maximum fault tolerance is found, and a fast replacement algorithm is given. The reconfiguration capability can also be used to ameliorate imbalanced traffic flows. The authors formulate this traffic flow assignment problem for the switch fabric and show that the problem is NP-hard. A simple heuristic algorithm is proposed, and an example is given 相似文献
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本文对符合IEEE802.4和MAP标准的令牌总线网的性能指标评估给出了一种新的计算方法。文中重点考虑了具有信包重发机制、令牌最大保留时间和信包缓冲区容量有限的令牌网络的性能指标评估问题,克服了以往不能分析同时具有信包重发机制和令牌最大保留时间令牌网性能的局限。文中给出的方法简单易行、计算迅速、精度颇高。最后,本文通过例题说明了此方法的应用。 相似文献