Novel droop-compensated comb decimation filter with improved alias rejections

This paper presents a novel two-stage comb decimator with the improved magnitude characteristic. Simple multiplierless corrector filters, which are designed using the frequency sampling and IFIR methods, are introduced. The proposed filters compensate the comb passband droop in the wideband passband region and increase the attenuations in the folding bands. Using the multirate identity the filters may be moved to a lower rate. The filter design depends only on the number of the cascaded comb filters and do not depend on the decimation factor M.     

SC filter for RF sampling and downconversion with wideband image rejection

In this paper we present an SC filter for RF downconversion using the direct RF sampling and decimation technique. The circuit architecture is generic and it features high image rejection for wideband signals and good linearity. An SC implementation in 0.13μm CMOS suitable for an RF of 2.4 GHz and 20 MHz signal bandwidth is presented as a demonstrator. Simulation results obtained using Cadence Spectre simulation tools are included.     

一种基于CIC滤波器的有效锐化方法研究

介绍了对积分梳状滤波器（CIC滤波器）的有效锐化。所提出的锐化滤波器的结构由两个主要部分组成：一个梳状滤波器的级联部分和一个锐化滤波器部分。所提出的方案使得滤波器中锐化部分的工作速率比输入速率大为降低，其频谱响应特性比传统的也有所改进。通过MATLAB仿真，可看出改进锐化后的滤波器性能更优。     

Lattice structure for arbitrary-length oversampled linear phase paraunitary filter bank with unequal numbers of symmetric and antisymmetric filters

Oversampled linear phase paraunitary filter bank (OLPPUFB) can be efficiently designed via lattice structure. Xu et al. have studied the lattice structure for arbitrary-length OLPPUFB (ALOLPPUFB), i.e. OLPPUFB with filter length KM + β, where M is the integer decimation factor, K is an integer, and β is an integer between 0 and M. Such work was restricted to be used for the case with equal numbers of symmetric and antisymmetric filters, and cannot be easily generalized for other possible cases. To address this issue, we develop in this letter the lattice structure for ALOLPPUFB with unequal numbers of symmetric and antisymmetric filters. The proposed method is carried out by combining the polyphase matrices of OLPPUFB with filter length KN, where N is the integer decimation factor, K is an integer. The efficiency of the method is shown by design examples.     

宽带∑-△A/D转换器中数字抽取滤波器的设计与验证

无线便携式移动设备与宽带intemet接入技术的发展,对∑-△A/D转化器的带宽要求越来越高。文中结合前端5阶宽带乏△调制器,设计了一种降低功耗与面积的数字抽取滤波器,应用于宽带高精度AD转换器中。MATLAB／simulink仿真结果表明,经过数字抽取滤波器滤波后信噪比为97．8dB,通带边界频率为1．8MHz,最小阻带衰减为70dB,通带内波纹0．0025dB,可满足设计要求。∑-△A/D转换器高精度、低功耗的优点,可广泛应用于中特种设备检验检测仪器仪表中。     

Fully synthesised decimation filter for delta-sigma A/D converters

Digital decimation filters are used in delta-sigma analogue-to-digital converters to reduce the oversampled data rate to the final Nyquist rate. This paper presents the design and implementation of a fully synthesised digital decimation filter that provides a time-to-market advantage. The filter consists of a cascaded integrator-comb filter and two cascaded half-band FIR filters. A canonical signed-digit representation of the filter coefficients is used to minimise the area and to reduce the hardware complexity of the multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated by using 0.25-μm CMOS technology with an active area of 1.36 mm² and shows 4.4 mW power consumption at a clock rate of 2.8224 MHz. Experimental results show that this digital decimation filter is suitable for use in oversampled data converters and can be applied to new processes requiring a fast redesign time. This is possible because the filter does not have process-dependent ROM or RAM circuits.     

一款高速、低功耗的Sigma-Delta模数转换器

提出了一种高速、低功耗、高分辨率的新型Sigma-Delta模数转换器(ADC)结构。该结构选择过采样率(OSR)为32的4阶调制器设计以缓解输出速率和通带宽度的压力,采用级联和双量化的方法进行优化,并利用SIMSIDES工具(基于Simulink的Sigma-Delta仿真器)进行仿真。数字抽取滤波器部分由级联积分梳状(CIC)滤波器、有限长单位冲激响应(FIR)滤波器和半带(HB)滤波器组成,并且三级滤波器都采用了多相分解结构,以降低动态功耗。使用0.18μm的标准CMOS工艺实现数字抽取滤波器版图。仿真结果表明,在250 kHz带宽下,有效位宽(ENOB)为19 bit。     

Double‐Sharpened Decimation Filter Employing a Pre‐droop Compensator for Multistandard Wireless Applications

This paper presents a double‐sharpened decimation filter based on the application of a Kaiser and Hamming sharpening technique for multistandard wireless systems. The proposed double‐sharpened decimation filter uses a pre‐droop compensator which improves the passband response of a conventional cascaded integrator‐comb filter so that it provides an efficient sharpening performance at half‐speed with comparison to conventional sharpened filters. In this paper, the passband droop characteristics with compensation provides –1.6 dB for 1.25 MHz, –1.4 dB for 2.5 MHz, –1.3 dB for 5 MHz, and –1.0 dB for 10 MHz bandwidths, respectively. These results demonstrate that the proposed double‐sharpened decimation filter is suitable for multistandard wireless applications.     

多相抽取滤波器的FPGA实现

信号的多相分解在多抽样率信号处理中有着重要的作用.介绍了多相分解的基本理论,结合FIR抽取滤波器的多相分解形式,用Verilog HDL语言来实现2倍抽取滤波器的多相结构,QuartusⅡ软件仿真输出波形,并且用MATLAB对仿真结果进行验证并作比较.结果正确,最后将编程数据文件下载到FPGA芯片上.多相抽取滤波器的设计方法是可行的,整个设计过程由软件实现,参数易于修改.     

An Applied Method for Designing Maximally Decimating Non-uniform Filter Banks

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一种应用于LTE协议的高速ΣΔADC的降采样滤波器

设计了一种应用于LTE协议的20 MHz带宽、12-bit精度ΣΔ模数转换器中的降采样低通数字滤波器,该滤波器采用一级梳状滤波器与两级半带滤波器级联的结构。基于低功耗设计考虑,降采样滤波器采用多相分解、CSD编码等技术,并对片内时钟偏差、串扰等进行优化以提高芯片的产率和可靠性。该设计在SMIC 00.13μm 1P8M标准CMOS工艺流片,测试结果表明芯片工作在11.2 V电源电压和500 MHz时钟频率时,在20 MHz的信号带宽内,带本滤波器的ΣΔADC的峰值SNDR和SNR分别为64.16 dB和64.71 dB,滤波器的功耗为4.8 mW。     

A new closed form method for design of variable bandwidth linear phase FIR filter using different polynomials

In this paper, a new method for the design of variable bandwidth linear-phase finite impulse response (FIR) filters using different polynomials such as shifted Chebyshev polynomials, Bernstein polynomials and shifted Legendre polynomials is proposed. For this purpose, the transfer function of a variable bandwidth filter, which is a linear combination of fixed-coefficient linear-phase filters and the above polynomials are separately exploited as tuning parameters to control bandwidth of the filter. In order to determine the filter coefficients, mean squared difference between the desired variable bandwidth filter and the practical filter is minimized by differentiating it with respect to its coefficients leading to a system of linear equations. The matrix elements can be expressed in form of Toeplitz-plus-Hankel matrix, which reduces the computational complexity. Several examples are included to demonstrate effectiveness of the proposed method in terms of passband error (e_p), stopband error (e_s) and stopband attenuation (A_s).     

宽带短波信道模拟器中数字下变频的实现

宽带短波信道模拟器是一种运用仿真技术对真实的短波信道进行模拟的仪器。首先指出数字下变频在宽带短波信道模拟器中的作用。然后,阐述了数字下变频中的数控振荡器、CIC滤波器、半带滤波器和低通滤波器的实现方法。最后,结合Matlab算法仿真技术,不依赖FPGA的IP核,设计并实现了基于FPGA的数字下变频。功能与时序仿真结果表明:基于FPGA设计实现的数字下变频能够满足宽带短波信道模拟器性能指标要求,并且具有灵活性、通用性和修改参数方便等特点。     

基于FPGA的极窄带滤波器的分析与设计

高性能极窄带滤波器是多普勒体制雷达接收机的关键功能模块。滤波器的设计除要求极窄的过渡带外,还需具备极大的镜频抑制比以及极小的带内失真。针对单速率以及包含抽取的多速率极窄带滤波器设计要求,分别提出了基于插值FIR滤波器的优化参数以及级联积分梳状（CIC）滤波器的性能曲线。在FPGA实现中进行了资源对比,采用文中给出的板窄带滤波器设计优化方法可达到最佳的资源性能比。最后基于滤波器IP核设计了高性能极窄带滤波器模块,具备很强的工程应用价值。     

一种改进的宽带数字下变频高效结构

该文首先分析了宽带数字下变频现有的高效结构能够实现高效性的根本原因及其存在的问题,接着通过公式推导求出新的实现方法:先抽取后滤波再用Goertzel滤波器实现混频过程直接获得同步调谐。通过与宽带数字下变频的一般结构和现有高效结构的比较,给出新结构的性能:对混频序列频点位置无任何限制、计算高效性、硬件复杂度适中。计算机仿真验证了新结构的有效性。     

一种16位音频∑△ A/D转换器

提出了一种16位立体声音频新型稳定的5阶∑△A/D转换器.该转换器由开关电容∑△调制器、抽取滤波器和带隙基准电路构成.提出了一种新的稳定高阶调制器的方法和一种新的梳状滤波器.采用0.5μm 5V CMOS工艺实现∑△A/D转换器.∑△A/D转换器可以得到96dB的峰值SNR,动态范围为96dB.整个芯片面积只有4.1mm×2.4mm,功耗为90mW.     

A 16-bit 250-kHz delta-sigma modulator and decimation filter

This paper describes a delta-sigma analog-to-digital converter (ADC) capable of converting input frequencies up to 250 kHz. It consists of a fifth-order switched-capacitor delta-sigma modulator and a decimation filter. Various design optimizations in the modulator are presented. The decimation filter consists of a comb filter followed by a novel, highly efficient and scalable finite impulse response filter. The ADC was implemented in 0.6-μm CMOS technology. It achieves a dynamic range of 94 db     

复信号多相滤波器的无盲区算法与FPGA设计

信道化和抽取技术是宽带数字信道化接收机中的关键技术。针对这一问题,首先分析了复信号多相滤波器无盲区算法及其数学模型,实现信号的全概率捕获。根据此数学模型,提出了复多相滤波器的FPGA设计方法。该方法根据模型中信道数与抽取倍数之间的关系,利用可定制模块和时序的配合完成了延迟和抽取功能;乘加单元完成多相分量的滤波运算;专用IP核完成FFT。整个模块采用乒乓RAM的设计思想和流水线结构。实验结果表明,该方法区别于一般旋转开关方法,能够实现信道数不等于抽取倍数的延迟和抽取．     

A design algorithm for optimal low-pass nonlinear phase FIR digital filters

The transfer function of the low-pass nonlinear phase finite impulse response (NLPFIR) digital filter is decomposed into a nonlinear phase part and a linear phase part. An algorithm is proposed to iteratively design the magnitude of the linear phase part and the squared magnitude of the nonlinear phase part by directly calling the Remez algorithm of McClellan, et al. [1]. In the design of the nonlinear phase part, we assume that the linearity constraint on the phase is dropped but the phase response is not specified. A scheme is incorporated into our algorithm so that it can design the filter with the desired ripple ratio. This approach also leads to a method for finding the minimum ripple ratio for the given orders of the two parts and band edges of the filters. The filters with ripple ratio larger than this minimum value can be designed by our algorithm and neither passband nor stopband ripples are required to be prescribed. Analysis of roundoff noise reveals that the cascade filter implementation usually needs higher wordlengths than its direct for counterpart for the same roundoff noise performance.     

无源双基地雷达动目标快速检测算法

在无源双基地雷达系统中,动目标的时延和多普勒频移估计是通过计算直达波信号和目标回波信号的互模糊函数来实现的。提出了首先利用级联积分梳状滤波器（CIC滤波器）对不同时延的互模糊函数进行抽取,然后进行FFT变换的动目标快速检测算法。CIC滤波器在数据抽取过程中能够有效抑制频率混叠干扰及通带信号衰减问题,同时由于信号采样频率的降低,FFT变换的频率分析范围将大大减小,从而明显提高信号处理速度。该算法可以从任意距离单元开始估计目标的多普勒频移,所以可以对数据进行并行处理,这将进一步提高信号检测和处理速度。最后,利用仿真数据验证了该算法的有效性。