Relationship between ADC performance and requirements of digital-IF receiver for WCDMA base-station

The recent rapid development of digital wireless systems has led to the need for multistandard, multichannel radiofrequency (RF) transceivers. The paper presents the relationship between the performance of a bandpass-sampling analog-to-digital converter (ADC) and the requirements of a digital intermediate-frequency receiver for a wideband code-division multiple-access (WCDMA) base-station. As such, the ADC signal-to-noise ratio (SNR), the derivation of the receiver sensitivity using the SNR/spurious free dynamic range (SFDR) of the ADC, the effect of the ADC clock jitter and receiver linearity, plus the relationship between the receiver IF and the ADC sampling frequency are all analyzed. As a result, when a WCDMA base-station receiver has a data rate of 12.2 kbps, bit error rate (BER) of 0.001, and channel index, k, of 5 (sampling frequency of 122.88 MHz and IF of 92.16 MHz), the performance of a bandpass-sampling ADC was analytically determined to require a resolution of 14 bits or more, SNR of 66.6 dB or more, SFDR of 86.5 dBc or more, and total jitter of 0.2 ps or less, including internal ADC jitters and clock jitters.     

An 80-MS/s 14-bit pipelined ADC featuring 83 dB SFDR

An 80-MS/s 14-bit pipelined analog-to-digital converter (ADC) is presented in this paper. After gain error and offset extraction from prototype measurement, the improved circuit achieves spurious free dynamic range (SFDR) of 82.9 dB and signal-to-noise-and-distortion ratio (SINAD) of 64.1 dB for a 30.5 MHz input, maintained within 6 dB performance deterioration up to 170 MHz input. Differential nonlinearity (DNL) is 0.66 LSB and integral nonlinearity (INL) is 2.5 LSB. Low-jitter clock amplifier and buffers with balanced loads are used to reduce the jitter and skew between different stages. An on-chip voltage reference generator is schemed with low impedance to reduce noise and spurs of reference signals. The ADC is fabricated in a 0.18-μm CMOS process with core area of 3.86 mm², and consumes 518 mW at 1.8 V supply.     

A 0.5-V 8-bit 10-Ms/s Pipelined ADC in 90-nm CMOS

This paper presents a pipelined analog-to-digital converter (ADC) operating from a 0.5-V supply voltage. The ADC uses true low-voltage design techniques that do not require any on-chip supply or clock voltage boosting. The switch OFF leakage in the sampling circuit is suppressed using a cascaded sampling technique. A front-end signal-path sample-and-hold amplifier (SHA) is avoided by using a coarse auxiliary sample and hold (S/H) for the sub-ADC and by synchronizing the sub-ADC and pipeline-stage sampling circuit. A 0.5-V operational transconductance amplifier (OTA) is presented that provides inter-stage amplification with an 8-bit performance for the pipelined ADC operating at 10 Ms/s. The chip was fabricated on a standard 90 nm CMOS technology and measures 1.2 mm times 1.2 mm. The prototype chip has eight identical stages and stage scaling was not used. It consumes 2.4 mW for 10-Ms/s operation. Measured peak SNDR is 48.1 dB and peak SFDR is 57.2 dB for a full-scale sinusoidal input. Maximal integral nonlinearity and differential nonlinearity are 1.19 and 0.55 LSB, respectively.     

A low power 12-b 40-MS/s pipeline ADC

This paper describes a 12-bit, 40-MS/s pipelined A/D converter (ADC) which is implemented in 0.18-μm CMOS process drawing 76-mW power from 3.3-V supply. Multi-bit architectures as well as telescopic operational transconductance amplifiers (OTAs) are adopted in all pipeline stages for good power efficiency. In the first two stages,particularly, 3-bit/stage architectures are used to improve the ADC's linearity performance. The ADC is calibration-free and achieves a DNL of less than 0.51 LSB and an INL of less than 1 LSB. The SNDR performance is above 67 dB below Nyquist. The 80-dB SFDR performance is maintained within 1 dB for input frequencies up to 49 MHz at full sampling rate.     

用于CMOS低中频GPS接收机的模数转换器的设计考虑与实现

首先对用于CMOS低中频GPS接收机的模数转换器(ADC)进行了设计考虑.由ADC引入的信噪比降低与四个因素有关:中频带宽,采样率,ADC的比特数及ADC的最大阈值与噪声均方根比值.在设计考虑的基础上,采用TSMC 0.25tan CMOS单层多晶硅五层金属工艺实现了一个4 bit 16.368 MHz闪烁型模数转换器,并将重点放在了前置放大器和提出的新的比较器的设计和优化上.在时钟采样率16.368 MHz和输入信号频率4.092 MHz的条件下,转换器测试得到的信噪失真比为24.7 dB,无杂散动态范围为32.1 dB,积分非线性为 0.31/-0.46LSB,差分非线性为 0.66/-0.46LSB,功耗为3.5mW.ADC占用芯片面积0.07 mm2.     

Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit

This paper describes an 8-bit 125 Mhzlow-powerCMOS fully-foldinganalog-to-digital converter(ADC).A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm~2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.     

A 90-nm CMOS, 8-bit pipeline ADC with 60-MHz bandwidth and 125-MS/s or 250-MS/s sampling frequency

In this paper a dual operating mode 8-bit, 1.1-V pipeline ADC for Gigabit Ethernet applications is presented. In the two operating modes, the ADC features different sampling frequency (125 and 250 MHz) and power consumption (9.4 and 22.8 mW). Considering a signal bandwidth of 60 MHz in both operating modes, as required by the Gigabit Ethernet standard, the ADC achieves a SNDR always larger than 39.4 dB at 125 MHz and 38.7 dB at 250 MHz (6.25-bit and 6.13-bit ENOB, respectively), with a FoM of 0.84 pJ/conv at 125 MHz and 2.2 pJ/conv at 250 MHz. The ENOB achieved is mainly limited by clock jitter. The ADC is fabricated with a 90-nm CMOS technology, with an active area of 1.25 × 0.65 mm².     

A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging

A 2-GS/s 6-bit ADC with time-interleaving is demonstrated in 0.18-/spl mu/m one-poly six-metal CMOS. A triple-cross connection method is devised to improve the offset averaging efficiency. Circuit techniques, enabling a state-of-the-art figure-of-merit of 3.5 pJ per conversion step, are discussed. The peak DNL and INL are measured as 0.32 LSB and 0.5 LSB, respectively. The SNDR and SFDR have achieved 36 and 48dB, respectively, with 4 MHz input signal. Near Nyquist input frequencies, the SNDR and SFDR maintain above 30 and 35.5dB, respectively, up to 941 MHz. The complete ADC, including front-end track-and-hold amplifiers and clock buffers, consumes 310 mW from a 1.8-V supply while operating at 2-GHz conversion rate. The prototype ADC occupies an active chip area of 0.5 mm/sup 2/.     

A CMOS switch-capacitor 14-bit 100 Msps pipeline ADC with over 90 dB SFDR

This article presents a design of 14-bit 100?Msamples/s pipelined analog-to-digital converter (ADC) implemented in 0.18?µm CMOS. A charge-sharing correction (CSC) is proposed to remove the input-dependent charge-injection, along with a floating-well bulk-driven technique, a fast-settling reference generator and a low-jitter clock circuit, guaranteeing the high dynamic performance of the ADC. A scheme of background calibration minimises the error due to the capacitor mismatch and opamp non-ideality, ensuring the overall linearity. The measured results show that the prototype ADC achieves spurious-free dynamic range (SFDR) of 91?dB, signal-to-noise-and-distortion ratio (SNDR) of 73.1?dB, differential nonlinearity (DNL) of +0.61/?0.57?LSB and integrated nonlinearity (INL) of +1.1/?1.0?LSB at 30?MHz input and maintains over 78?dB SFDR and 65?dB SNDR up to 425?MHz, consuming 223?mW totally.     

一种具有采样带宽补偿的高性能采样/保持电路

针对中频采样模数装换器中的宽带采样/保持电路,提出了一种新颖的电荷交换补偿（CEC）技术.该技术通过消除采样开关有限导通电阻的影响,补偿了采样带宽,并避免了时钟馈通和电荷注入的加剧.同时设计了具有AB类输出的低功耗两级运放,在1.8V电源下为该采样/保持提供了3V峰-峰值的输入范围.该采样/保持电路在100Ms/s的采样率下,对于200MHz输入信号达到了94dB的无杂散动态范围.在5.5pF的负载下,功耗仅为26mW.     

一种具有采样带宽补偿的高性能采样/保持电路

针对中频采样模数装换器中的宽带采样/保持电路,提出了一种新颖的电荷交换补偿(CEC)技术.该技术通过消除采样开关有限导通电阻的影响,补偿了采样带宽,并避免了时钟馈通和电荷注入的加剧.同时设计了具有AB类输出的低功耗两级运放,在1.8V电源下为该采样/保持提供了3V峰-峰值的输入范围.该采样/保持电路在100Ms/s的采样率下,对于200MHz输入信号达到了94dB的无杂散动态范围.在5.5pF的负载下,功耗仅为26mW.     

A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive read-channelapplications

The analog-to-digital conversion required in most disk-drive read-channel applications is designed for good dynamic and noise performance over a wide-input frequency range. This paper presents a 500-MSample/s, 6-bit analog to-digital converter (ADC) and its embedded implementation inside a disk-drive read channel, using a 0.35-μm CMOS double-poly (only one poly layer was used in the ADC), triple-metal process. The converter achieves better than 5 effective number of bits (ENOB) for input frequencies up to Nyquist frequency (f_in=f _s/2) and sampling frequencies f_s up to 400 MHz. It also achieves better that 5.6 ENOB for input frequencies up to f_s /4 over process, temperature, and power-supply variations. At maximum speed (f_s=500 MHz), the converter still achieves better than 5 ENOB for input frequencies up to f_in=200 MHz. Low-frequency performance is characterized by DNL<0.32 LSB and INL<0.2 LSB. The converter consumes 225 mW from a 3.3-V supply when running at 300 MHz and occupies 0.8 mm² of chip area     

采用改进型1.5位/级结构的10位100MHz流水线模数转换器

介绍了一个采用改进型1.5位/级结构的10位100MHz流水线结构模数转换器.测试结果表明,模数转换器的信噪失真比最高可以达到57dB,在100MHz输入时钟下,输入信号为57MHz的奈奎斯特频率时,信噪失真比仍然可以达到51dB.模数转换器的差分非线性和积分非线性分别为0.3LSB和1.0LSB.电路采用0.18μm混合信号CMOS工艺实现,芯片面积为0.76mm2.     

A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications

This paper describes a 10-bit 30-MS/s subsampling pipelined analog-to-digital converter (ADC) that is implemented in a 0.18 mum CMOS process. The ADC adopts a power efficient amplifier sharing architecture in which additional switches are introduced to reduce the crosstalk between the two opamp-sharing successive stages. A new configuration is used in the first stage of the ADC to avoid using a dedicated sample-and-hold amplifier (SHA) circuit at the input and to avoid the matching requirement between the first multiplying digital-to-analog converter (MDAC) and flash input signal paths. A symmetrical gate-bootstrapping switch is used as the bottom-sampling switch in the first stage to enhance the sampling linearity. The measured differential and integral nonlinearities of the prototype are less than 0.57 least significant bit (LSB) and 0.8 LSB, respectively, at full sampling rate. The ADC exhibits higher than 9.1 effective number of bits (ENOB) for input frequencies up to 30 MHz, which is the twofold Nyquist rate (fs/2), at 30 MS/s. The ADC consumes 21.6 mW from a 1.8-V power supply and occupies 0.7 mm², which also includes the bandgap and buffer amplifiers. The figure-of-merit (FOM) of this ADC is 0.26 pJ/step.     

A power-efficient 10-bit 40-MS/s sub-sampling pipelined CMOS analog-to-digital converter

This paper presents a 10-bit 40-MS/s pipelined analog-to-digital converter (ADC) in a 0.13-μm CMOS process for subsampling applications. A simplified opamp-sharing scheme between two successive pipelined stages is proposed to reduce the power consumption. For subsampling, a cost-effective fast input-tracking switch with high linearity is introduced to sample the input signal up to 75 MHz. A two-stage amplifier with hybrid frequency compensation is developed to achieve both high bandwidth and large swing with low power dissipation. The measured result shows that the ADC achieves over 77 dB spurious free dynamic range (SFDR) and 57.3 dB signal-to-noise-plus-distortion ratio (SNDR) within the first Nyquist zone and maintains over 70 dB SFDR and 55.3 dB SNDR for input signal up to 75 MHz. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.2 LSB and ±0.3 LSB, respectively. The ADC consumes 15.6 mW at the sampling rate of 40 MHz from a 1.2-V supply voltage, and achieves a figure-of-merit (FOM) value of 0.22 pJ per conversion step.     

A 1.2 V 10-bit 5MS/s low power CMOS cyclic ADC based on double-sampling technique

This paper presents a 1.2 V 10-bit 5MS/s low power cyclic analog-to-digital converter (ADC). The strategy to minimize the power adopts the double-sampling technique. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit (S/H) is employed to enhance the dynamic performance of the cyclic ADC. Double sampling technique is also applied to multiplying digital-to-analog converter (MDAC). This scheme provides a better power efficiency for the proposed cyclic ADC. Furthermore, bootstrapped switch is used to achieve rail-to-rail signal swing at low-voltage power supply. The prototype ADC, fabricated in TSMC 0.18 μm CMOS 1P6 M process, achieves DNL and INL of 0.32LSB and 0.45LSB respectively, while SFDR is 69.1 dB and SNDR is 58.6 dB at an input frequency of 600 kHz. Operating at 5MS/s sampling rate under a single 1.2 V power supply, the power consumption is 1.68 mW.     

Oversampled pipeline A/D converters with mismatch shaping

This paper presents a pipeline analog-to-digital converter (ADC) with improved linearity. The linearity improvement is achieved through a combination of oversampling and mismatch shaping, which modulates the distortion energy out of band. Mismatch shaping can be realized in a traditional 1-bit/stage pipeline ADC, but the ADCs transfer characteristic properties limit its effectiveness at pushing the distortion out of band. These limitations can be alleviated by using a 1-bit/stage commutative feedback capacitor switching pipeline design. A test chip was fabricated in a 0.35-μm CMOS process to demonstrate mismatch shaping. Experimental results obtained indicate that the spurious-free dynamic range improves by 8.5 dB to 76 dB when mismatch shaping is used at an oversampling ratio of 4 and a sampling rate of 61 MHz. The signal-to-noise and distortion ratio improves by 3 dB and the maximum integral nonlinearity decreases from 1.8 to 0.6 LSB at the 12-bit level     

A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer

A 12-bit 30 MSPS pipeline analog-to-digital converter(ADC) implemented in 0.13-μm 1P8M CMOS technology is presented.Low power design with the front-end sample-and-hold amplifier removed is proposed.Except for the first stage,two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption.The ADC presents 65.3 dB SNR,75.8 dB SFDR and 64.6 dB SNDR at 5 MHz analog input with 30.7 MHz sampling rate.The chip dissipates 33.6 mW from 1.2 V power supply.FOM is 0.79 pJ/conv step.     

An 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter in SiGe technology

This paper deals with the design and implementation of an 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter (ADC) using a SiGe technology with a unity gain cutoff frequency f/sub T/ of 47 GHz. The high-speed high-resolution ADC has applications in direct IF sampling receivers for wideband communication systems. The converter occupies an area of 3.5 mm/spl times/3.5 mm including pads and exhibits an effective resolution bandwidth of 700 MHz at a sampling rate of 2 Gsample/s. The maximum DNL and INL are 0.5 and 1 LSB, respectively. The ADC dissipates 3.5W (including output buffers) from a 3.3-V power supply.     

A 16-bit 65-MS/s 3.3-V pipeline ADC core in SiGe BiCMOS with 78-dB SNR and 180-fs jitter

The analog-to-digital converter presented in this work demonstrates the efficiency of the straight 2.5 bit-per-stage approach for the implementation of pipelined switched-capacitor architectures targeting up to 16-bit resolution and 65-MS/s sampling rate. The test chip has been fabricated in a 45-GHz f/sub T/, 0.4-/spl mu/m 3.3-V SiGe BiCMOS process that makes it suitable for integration with an RF front-end toward an antenna-to-DSP communication processor. Performance of 78.3 dBFS SNR, 88dBc SFDR at 65 MS/s, 1 MHz input is obtained without trimming or calibration, dissipating 970 mW total with external references. Since the 4 V/sub p-p/ signal range chosen for high SNR could lead to distortion in the Sample/Hold and the pipelined quantizer with only 3.3-V supply, a fast and accurate SPICE simulation technique for INL investigation is described that enabled detailed diagnosis of potential nonlinearity sources. Theoretical analysis and practical implementation of the clock circuit are also discussed allowing the design of a CMOS-based clock featuring 180-fs jitter, which preserves high SNR against input frequency: state-of-the-art 73.5dBFS have been observed at 150 MHz input, popular intermediate frequency (IF) for single-heterodyne BTS receivers. Finally, the figures of merit encompassing power, effective resolution, and speed rank the dynamic performance of the ADC core among the best in its class.