碳化硅MOSFET电学参数的电容-电阻法评估

阈值电压、栅内阻、栅电容是碳化硅(SiC)金属氧化物半导体场效应晶体管(MOSFET)的重要电学参数,但受限于器件寄生电阻、栅介质界面态等因素,其提取过程较为复杂且容易衍生不准确性。文章通过器件建模和实验测试,揭示了MOSFET的栅电容非线性特征,构建了电容-电阻串联电路测试方法,研究了SiC MOSFET的栅内阻和阈值电压特性。分别获得栅极阻抗和栅源电压、栅极电容和栅源电压的变化规律,得到栅压为-10V时的栅内阻与目标值误差小于0.5Ω,以及串联电容相对栅源电压变化最大时的电压近似为器件阈值电压。相关结果与固定电流法作比较,并分别在SiC平面栅和沟槽栅MOSFET中得到验证。因此,该种电容-电阻法为SiC MOSFET器件所面临的阈值电压漂移、栅极开关振荡现象提供较为便捷的评估和预测手段。     

新型双异质结双平面掺杂功率PHEMT

设计并制作了双异质结双平面掺杂的Al0.24Ga0.76As/In0.22Ga0.78As/Al0.24Ga0.76As功率PHEMT器件,采用双选择腐蚀栅槽结构,有效提高了PHEMT器件的输出电流和击穿电压.对于1μm栅长的器件,最大输出电流为500mA/mm,跨导为275mS/mm,阈值电压为-1.4V,最大栅漏反向击穿电压达到了33V.研究结果表明,在栅源间距一定时,栅漏间距对于器件的输出电流、跨导和击穿电压有很大关系,是设计功率PHEMT的关键之一.     

一种P-GaN栅结合混合帽层结构的HEMT器件

为了进一步提升P-GaN栅HEMT器件的阈值电压和击穿电压,提出了一种具有P-GaN栅结合混合掺杂帽层结构的氮化镓高电子迁移率晶体管(HEMT)。新器件利用混合掺杂帽层结构,调节整体极化效应,可以进一步耗尽混合帽层下方沟道区域的二维电子气,提升阈值电压。在反向阻断状态下,混合帽层可以调节栅极右侧电场分布,改善栅边电场集中现象,提高器件的击穿电压。利用Sentaurus TCAD进行仿真,对比普通P-GaN栅增强型器件,结果显示,新型结构器件击穿电压由593 V提升至733 V,增幅达24%,阈值电压由0.509 V提升至1.323 V。     

凹槽栅场调制板结构AlGaN/GaN HEMT

研制的SiC衬底上的AlGaN/GaN微波功率HEMTs,采用凹槽栅和场调制板结构有效抑制了器件的电流崩塌,提高了器件的击穿电压和器件的微波功率特性.研制的1mm栅宽器件在8GHz,34V工作电压下,饱和输出功率达到了9.05W,功率增益为7.5dB,功率附加效率为46%.     

凹槽栅场调制板结构AlGaN/GaN HEMT

研制的SiC衬底上的AlGaN/GaN微波功率HEMTs,采用凹槽栅和场调制板结构有效抑制了器件的电流崩塌,提高了器件的击穿电压和器件的微波功率特性.研制的1mm栅宽器件在8GHz,34V工作电压下,饱和输出功率达到了9.05W,功率增益为7.5dB,功率附加效率为46%.     

一种200V/100A VDMOS器件开发

分析了功率MOSFET最大额定电流与导通电阻的关系,讨论了平面型中压大电流VDMOS器件设计中导通电阻、面积和开关损耗的折衷考虑,提出了圆弧形沟道布局以增大沟道宽度,以及栅氧下部分非沟道区域采用局域氧化技术以减小栅电容的方法,并据此设计了一种元胞结构。详细论述了器件制造过程中的关键工艺环节,包括栅氧化、光刻套准、多晶硅刻蚀、P阱推进等。流水所得VDMOS实测结果表明,该器件反向击穿特性良好,栅氧耐压达到本征击穿,阈值电压2.8V,导通电阻仅25mΩ,器件综合性能良好。     

1700V碳化硅MOSFET设计

设计了一种击穿电压大于1 700V的SiC MOSFET器件。采用有限元仿真的方法对器件的外延掺杂浓度及厚度、有源区结构以及终端保护效率进行了优化。器件采用14μm厚、掺杂浓度为5×1015cm-3的N型低掺杂区。终端保护结构采用保护环结构。栅压20V、漏压2V时,导通电流大于1A,击穿电压高于1 800V。     

新型双异质结双平面掺杂功率PHEMT

设计并制作了双异质结双平面掺杂的Al0 .2 4 Ga0 .76 As/ In0 .2 2 Ga0 .78As/ Al0 .2 4 Ga0 .76 As功率PHEMT器件,采用双选择腐蚀栅槽结构,有效提高了PHEMT器件的输出电流和击穿电压.对于1μm栅长的器件,最大输出电流为5 0 0 m A/ mm ,跨导为2 75 m S/ m m,阈值电压为- 1 .4 V,最大栅漏反向击穿电压达到了33V .研究结果表明,在栅源间距一定时,栅漏间距对于器件的输出电流、跨导和击穿电压有很大关系,是设计功率PHEMT的关键之一.     

一种P-GaN栅极结合槽栅技术的增强型HEMT

为了得到高击穿电压、高阈值电压的增强型GaN器件,提出了一种P型掺杂GaN(P-GaN)栅极结合槽栅技术的AlGaN/GaN/AlGaN双异质结结构。该器件的阈值电压高达3.4 V,击穿电压达738 V。利用Sentaurus TCAD进行仿真,对比了传统P-GaN栅与P-GaN栅结合槽栅的AlGaN/GaN/AlGaN双异质器件的阈值电压和耐压。结果表明,栅槽深度在5~13 nm范围内变化时,阈值电压随栅槽深度的增大而增大,击穿电压随栅槽深度的增大呈先增大后略减小;导通电阻随槽栅深度的增大而增大,最小导通电阻为11.3 Ω·mm。     

中压沟槽MOSFET的设计与研究

基于仿真和实验方法,开展了100VN沟槽MOSFET的设计研究工作.通过沟槽深度,体区注入剂量和栅氧化层厚度拉偏,获得了对击穿电压,阈值电压和导通电阻的影响规律并对机理进行了分析,仿真工具同时描述了器件内部的电流路径和碰撞电离率分布.随着沟槽深度增加击穿电压先升后降,导通电阻则表现为相反趋势;击穿电压与注入剂量具有弱相关性,阈值电压随注入剂量增加而升高;击穿电压随着栅氧化层厚度增加整体表现上升趋势,但变化幅度不大,阈值电压与厚度变化表现出强相关性.通过逐步优化获得了最终结构和工艺参数为沟槽深度1.5μm,体区注入剂量1.3E13,栅氧化层厚度700 A,通过流片获得器件最终电性参数为击穿电压为105.6 V,阈值电压2.67 V,导通电阻3.12 mR,相较于仿真参数分别有98%,94%和75%的变化率.     

1200V/100A高温大电流4H-SiC JBS器件的研制

基于SiC结势垒肖特基(JBS)二极管工作原理及其电流/电场均衡分布理论,采用高温大电流单芯片设计技术及大尺寸芯片加工技术,研制了1 200 V/100 A高温大电流4H-SiCJBS二极管.该器件采用优化的材料结构、有源区结构和终端结构,有效提高了器件的载流子输运能力.测试结果表明,当正向导通压降为1.60 V时,其正向电流密度达247 A/cm2(以芯片面积计算).在测试温度25和200℃时,当正向电流为100 A时,正向导通压降分别为1.64和2.50 V;当反向电压为1 200 V时,反向漏电流分别小于50和200μA.动态特性测试结果表明,器件的反向恢复特性良好.器件均通过100次温度循环、168 h的高温高湿高反偏(H3TRB)和高温反偏可靠性试验,显示出优良的鲁棒性.器件的成品率达70％以上.     

碳化硅MOSFET反型沟道迁移率的研究

SiC MOSFET是制作高速、低功耗开关功率器件的理想材料，然而，制作反型沟道迁移率较高的SiC MOSFET工艺尚未取得满意结果。通过在N0中高温退火可以显著地提高4H—SiC MOSFET的有效沟道迁移率；采用H2中退火制作的4H—SiC MOSFET阈值电压为3．1V，反型沟道迁移率高于100cm^2／Vs的栅压的安全工作区较宽。N20退火技术由于其的安全性而发展迅速并将取代N0。     

SiC JBS二极管和SiC MOSFET的空间辐照效应及机理

基于第六代650 V 碳化硅结型肖特基二极管(SiC JBS Diode)和第三代900 V 碳化硅场效应晶体管(SiC MOSFET),开展SiC功率器件的单粒子效应、总剂量效应和位移损伤效应研究。20~80 MeV质子单粒子效应实验中,SiC功率器件发生单粒子烧毁(SEB)时伴随着波浪形脉冲电流的产生,辐照后SEB器件的击穿特性完全丧失。SiC功率器件发生SEB时的累积质子注量随偏置电压的增大而减小。利用计算机辅助设计工具(TCAD)开展SiC MOSFET的单粒子效应仿真,结果表明,重离子从源极入射器件时,具有更短的SEB发生时间和更低的SEB阈值电压。栅-源拐角和衬底-外延层交界处为SiC MOSFET的SEB敏感区域,强电场强度和高电流密度的同时存在导致敏感区域产生过高的晶格温度。SiC MOSFET在栅压偏置(U_GS=3 V,U_DS=0 V)下开展钴源总剂量效应实验,相比于漏压偏置(U_GS=0 V,U_DS=300 V)和零压偏置(U_GS=U_DS=0 V),出现更严重的电学性能退化。利用中带电压法分析发现,栅极偏置下氧化层内的垂直电场提升了陷阱电荷的生成率,加剧了阈值电压的退化。中子位移损伤会导致SiC JBS二极管的正向电流和反向电流减小。在漏极偏置下进行中子位移损伤效应实验,SiC MOSFET的电学性能退化最严重。该研究为空间用SiC器件的辐射效应机理及抗辐射加固研究提供了一定的参考和支撑。     

SiO2/4H-SiC界面氮化退火

通过1 300℃高温干氧热氧化法在n型4H-SiC外延片上生长了厚度为60 nm的SiO2栅氧化层.为了开发适合于生长低界面态密度和高沟道载流子迁移率的SiC MOSFET器件产品的栅极氧化层退火条件,研究了不同退火条件下的SiO2/SiC界面电学特性参数.制作了MOS电容和横向MOSFET器件,通过表征SiO2栅氧化层C-V特性和MOSFET器件I-V特性,提取平带电压、C-V磁滞电压、SiO2/SiC界面态密度和载流子沟道迁移率等电学参数.实验结果表明,干氧氧化形成SiO2栅氧化层后,在1 300℃通入N2退火30 min,随后在相同温度下进行NO退火120 min,为最佳栅极氧化层退火条件,此时,SiO2/SiC界面态密度能够降低至2.07×1012 cm-2·eV-1@0.2 eV,SiC MOSFET沟道载流子迁移率达到17 cm2·V-1·s-1.     

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (V_t) drops resulting in a much higher current drive than standard MOSFET for low-power supply voltages. On the other hand, V_t is high at V_gs=0, therefore the leakage current is low. We provide extensive experimental results and two-dimensional (2-D) device and mixed-mode simulations to analyze this device and compare its performance with a standard MOSFET. These results verify excellent inverter dc characteristics down to V_dd=0.2 V, and good ring oscillator performance down to 0.3 V for Dynamic Threshold-Voltage MOSFET (DTMOS)     

UHF频段高功率SiC SIT

采用导通SiC衬底上的SiC多层外延材料,成功制作出了国内首个SiC SIT(静电感应晶体管).该器件研制中,采用了自对准工艺、高能离子注入及高温退火工艺、密集栅深凹槽干法刻蚀工艺、PECVD SiO:和SizNy介质钝化工艺,有效抑制了漏电并提高了器件击穿电压,器件功率输出能力由此得到提升.最终28 cm栅宽SiC ...     

Dynamic threshold voltage damascene metal gate MOSFET (DT-DMG-MOS)technology for very low voltage operation of under 0.7 V

We propose dynamic threshold-voltage damascene metal gate MOSFET (DT-DMG-MOS) technology for very low voltage operation (under 0.7 V). In this technology the metal gate is formed by the damascene gate process and directly connected to the well region (Si-body). Therefore, the connection between gate electrode and silicon body can be more easily fabricated in the DT-DMG transistor than with conventional technologies. Furthermore, we found that low threshold voltage (about 0.15 V reduction for CMOS), high drive current, excellent subthreshold swing (about 60 mV/decade), and uniform electrical characteristics (great reduction of threshold voltage deviation) were obtained in the transistors with midgap work function metal gates (Al/TiN or W/TiN) and low supply voltage (0.7 V)     

A nonvolatile semiconductor memory device in 6H-SiC for harsh environment applications

An electrically erasable programmable read-only memory (EEPROM) cell fabricated on a 6H-SiC substrate is reported. It is the first fully functional SiC EEPROM device. This device uses a generic double-polysilicon-gate configuration. It has been tested at both room temperature and elevated temperatures, up to 200/spl deg/C, to demonstrate full programmability. The threshold voltage shifts between programmed and erased states, at all tested temperatures, are larger than 4.5 V. In both states, the device functions satisfactorily as an n-type MOSFET. Charge retention time is more than 24 h at room temperature.     

SiC devices: physics and numerical simulation

The important material parameters for 6H silicon carbide (6H-SiC) are extracted from the literature and implemented into the 2-D device simulation programs PISCES and BREAKDOWN and into the 1-D program OSSI Simulations of 6H-SiC p-n junctions show the possibility to operate corresponding devices at temperatures up to 1000 K thanks to their low reverse current densities. Comparison of a 6H-SiC 1200 V p-n^--n⁺ diode with a corresponding silicon (Si) diode shows the higher switching performance of the 6H-SiC diode, while the forward power loss is somewhat higher than in Si due to the higher built-in voltage of the 6H-SiC p-n junction. This disadvantage can be avoided by a 6H-SiC Schottky diode. The on-resistances of Si, 3C-SiC, and 6H-SiC vertical power MOSFET's are compared by analytical calculations. At room temperature, such SiC MOSFET's can operate up to blocking capabilities of 5000 V with an on-resistance below 0.1 Ωcm², while Si MOSFET's are limited to below 500 V. This is checked by calculating the characteristics of a 6H-SiC 1200 V MOSFET with PISCES. In the voltage region below 200 V, Si is superior due to its higher mobility and lower threshold voltage. Electric fields in the order of 4×10⁶ V/cm occur in the gate oxide of the mentioned 6H-SiC MOSFET as well as in a field plate oxide used to passivate its planar junction. To investigate the high frequency performance of SiC devices, a heterobipolartransistor with a 6H-SiC emitter is considered. Base and collector are assumed to be out of 3C-SiC. Frequencies up to 10 GHz with a very high output power are obtained on the basis of analytical considerations     

A dynamic threshold voltage MOSFET (DTMOS) for very low voltageoperation

A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than regular MOSFET at low V_dd. On the other hand, V_t is high at V_gs =0, thus the leakage current is low. Suitability of this device for ultra low voltage operation is demonstrated by ring oscillator performance down to V_dd=0.5 V