无结器件的单粒子辐射效应

介绍了一种新型沟道非均匀掺杂的双栅无结金属氧化物半导体场效应晶体管(MOSFET)。采用Sentaurus TCAD仿真软件对不同沟道掺杂浓度(NSC)的沟道非均匀掺杂双栅无结MOSFET和传统双栅无结MOSFET进行了电特性与单粒子辐射效应对比研究,并分析了不同源端沟道掺杂与源端沟道长度(LSC)下新型双栅无结MOSFET的单粒子辐射特性。仿真结果表明,新型双栅无结MOSFET的电学特性与传统双栅无结MOSFET相差不大,但在抗单粒子辐射方面具有优良的性能,在受到单粒子辐射时,可有效降低沟道内电子-空穴对的产生概率,漏极电流与收集电荷都低于传统无结器件,同时还可以降低寄生三极管效应对器件的影响。     

Ge/SiGe异质结构肖特基源漏MOSFET

制备了氧化铪(HfO2)高k介质栅Si基Ge/SiGe异质结构肖特基源漏场效应晶体管(SB-MOSFET)器件,研究了n型掺杂Si0.16Ge0.84层对器件特性的影响,分析了n型掺杂SiGe层降低器件关态电流的机理。使用UHV CVD沉积系统,采用低温Ge缓冲层技术进行了材料生长,首先在Si衬底上外延Ge缓冲层,随后生长32 nm Si0.16Ge0.84和12 nm Ge,并生长1 nm Si作为钝化层。使用原子力显微镜和X射线衍射对材料形貌和晶体质量进行表征,在源漏区沉积Ni薄膜并退火形成NiGe/Ge肖特基结,制备的p型沟道肖特基源漏MOSFET,其未掺杂Ge/SiGe异质结构MOSFET器件的空穴有效迁移率比相同工艺条件制备的硅器件的高1.5倍,比传统硅器件空穴有效迁移率提高了80%,掺杂器件的空穴有效迁移率与传统硅器件的相当。     

截止频率53GHz的高性能0.18μm射频nMOSFET

阐述了0.18μm射频nMOSFET的制造和性能.器件采用氮化栅氧化层/多晶栅结构、轻掺杂源漏浅延伸结、倒退的沟道掺杂分布和叉指栅结构.除0.18μm的栅线条采用电子束直写技术外,其他结构均通过常规的半导体制造设备实现.按照简洁的工艺流程制备了器件,获得了优良的直流和射频性能:阈值电压0.52V,亚阈值斜率80mV/dec,漏致势垒降低因子69mV/V,截止电流0.5nA/μm,饱和驱动电流458μA/μm,饱和跨导212μS/μm(6nm氧化层,3V驱动电压)及截止频率53GHz.     

截止频率53GHz的高性能0.18μm射频nMOSFET

阐述了0.18μm射频nMOSFET的制造和性能.器件采用氮化栅氧化层/多晶栅结构、轻掺杂源漏浅延伸结、倒退的沟道掺杂分布和叉指栅结构.除0.18μm的栅线条采用电子束直写技术外,其他结构均通过常规的半导体制造设备实现.按照简洁的工艺流程制备了器件,获得了优良的直流和射频性能:阈值电压0.52V,亚阈值斜率80mV/dec,漏致势垒降低因子69mV/V,截止电流0.5nA/μm,饱和驱动电流458μA/μm,饱和跨导212μS/μm(6nm氧化层,3V驱动电压)及截止频率53GHz.     

基于HfO2栅介质的Ga2O3 MOSFET器件研制

采用金属有机化学气相沉积(MOCVD)方法在(010) Fe掺杂半绝缘Ga2O3同质衬底上外延得到n型β-Ga2O3薄膜材料,材料结构包括400 nm的非故意掺杂Ga2O3缓冲层和40 nm的Si掺杂Ga2O3沟道层.基于掺杂浓度为2.0×1018 cm-3的n型β-Ga2O3薄膜材料,采用原子层沉积的25 nm的HfO2作为栅下绝缘介质层,研制出Ga2O3金属氧化物半导体场效应晶体管(MOSFET).器件展示出良好的电学特性,在栅偏压为8V时,漏源饱和电流密度达到42 mA/mm,器件的峰值跨导约为3.8 mS/mm,漏源电流开关比达到108.此外,器件的三端关态击穿电压为113 V.采用场板结构并结合n型Ga2O3沟道层结构优化设计能进一步提升器件饱和电流和击穿电压等电学特性.     

A High Performance 0.18μm RF nMOSFET with 53GHz Cutoff Frequency

阐述了0.18μm射频nMOSFET的制造和性能. 器件采用氮化栅氧化层/多晶栅结构、轻掺杂源漏浅延伸结、倒退的沟道掺杂分布和叉指栅结构. 除0.18μm的栅线条采用电子束直写技术外，其他结构均通过常规的半导体制造设备实现. 按照简洁的工艺流程制备了器件，获得了优良的直流和射频性能：阈值电压0.52V，亚阈值斜率80mV/dec，漏致势垒降低因子69mV/V，截止电流0.5nA/μm，饱和驱动电流458μA/μm，饱和跨导212μS/μm (6nm氧化层，3V驱动电压）及截止频率53GHz.     

采用有限元方法研究轻掺杂源漏结构对异质栅MOSFET的性能影响(英文)

提出了一种轻掺杂源漏结构结合异质材料双栅结构的MOSFET(简称LDDS-HMG-MOSFET)。使用二维非平衡格林函数(NEGF)对该结构进行仿真,其中非平衡格林函数的计算使用有限元法(FEM)。仿真结果表明,在该新型结构中,异质栅结构能够降低漏电流从而能够有效抑制漏极感应势垒较低效应(DIBL),LDDS结构能够增加有效栅长,有效抑制带带隧穿效应(BTBT)和热电子效应。因此,与传统单材料栅结构的MOSFET(简称C-MOSFET)相比,LDDS-HMG-MOSFET具有更加优越的性能、更低的漏电流和更大的开关电流比(Ion/Ioff)。     

掺杂分布对EPROM编程的影响

在EPROM器件中,栅注入电流Ig对于Si表面的可动电子浓度n和电场E非常敏感。我们用二维电子温度器件模拟程序研究了n、E和Ig与掺杂分布的关系。 我们研究了沟长L=2(μm)、浮置栅氧化层厚度T_(ox)=400(?)的双栅EPROM器件。漏极写入电压采用17V,产生的漏电流为1.2mA。我们在一个等效的MOSFET上调节栅电压,以便使漏电流I_d与这一写电流相等,发现三种不同的沟道分布的浮置栅压(V_(gf))当量为12.8V、13.9V和16V。     

一种用于亚微米多晶栅TiSi电阻优化的方法

在亚微米工艺中,多晶栅TiSi工艺是降低接触电阻的常用方法。但是TiSi的生长与衬底的掺杂浓度相关,对多晶栅的掺杂剂量有很高的要求。由于光刻工艺中存在的套刻偏差,使得后续源漏注入剂量会在多晶栅上有所偏差,影响了后续TiSi在多晶栅上的生长。文章采用多晶栅上生长一层LPCVD SiN作为掩蔽层的方法,避免了由于光刻套刻偏差引入的注入剂量偏差,改善了后续多晶栅上TiSi的生长。通过对As注入和P注入在不同SiN厚度掩蔽层下穿透率的研究发现40 nm左右基本可以阻挡95%的N+S/D As注入剂量而保留80%的多晶栅P注入剂量。该种掩蔽层方法有很多优点:源漏注入的条件不用更改;多晶栅注入的可调节剂量范围大大增加,可以更好地保持重掺杂多晶栅特性。     

用气态源分子束外延生长法制备Si/SiGe/Si nPn异质结双极晶体管

用气态源分子束外延法制备了Si/SiGe/Si npn异质结双极晶体管.晶体管基区Ge组分为0.12,B掺杂浓度为1.5×101 9cm-3, SiGe合金厚度约45nm.直流特性测试表明,共发射极直流放大倍数约50,击穿电压VCE约9V;射频特性测试结果表明,晶体管的截止频率为7GHz,最高振荡频率为2.5GHz.     

Dynamic performance of graded channel DG FD SOI n-MOSFETs for minimizing the gate misalignment effect

Double gate MOSFET has been regarded as the most promising candidate for future CMOS devices, for excellent short channel effects (SCEs) immunity and high current drivability due to double gate coupling. The alignment between the top and bottom gates should be concern to fully realize the benefits of the double-gate configuration, as gate misalignment causes degradation in the device performance. Use of graded channel architectures somehow reduces the effect of gate misalignment. We scrutinize that how the misalignment affects the small signal behavior and device characteristics like conductances, capacitances and cut-off frequency, for uniformly doped and graded channel double gate architectures. Considering the fact that gate misalignment can occur on any side of the gate, extensive simulations have been carried out using high-low (H-L), low-high (L-H) and low-high-low (L-H-L) doping profiles for both source (DGS) and drain side (DGD) gate misalignment.     

Cut-off frequency and transit time analysis in short geometry polysilicon thin-film transistors

An accurate model for the drain characteristics, transconductance, cut-off frequency and transit time of a short geometry polysilicon thin film transistor (poly-Si TFT) is presented. An accurate threshold voltage and field dependent mobility are the key parameters in determining the above-threshold characteristics. The current-voltage characteristics of the device show an excellent agreement with experimental results. The transconductance for both linear and saturation regions is calculated and its variation with channel length, drain and gate voltages is studied. The total gate capacitance including the geometric capacitance and the fringing capacitance is also evaluated and simple closed form expressions for the cut-off frequency and transit time are obtained. A high cut-off frequency is achieved, which is important in realizing the device for millimetre and microwave frequency applications.     

DC and analog/RF performance optimisation of source pocket dual work function TFET

We investigate a systematic study of source pocket tunnel field-effect transistor (SP TFET) with dual work function of single gate material by using uniform and Gaussian doping profile in the drain region for ultra-low power high frequency high speed applications. For this, a n⁺ doped region is created near the source/channel junction to decrease the depletion width results in improvement of ON-state current. However, the dual work function of the double gate is used for enhancement of the device performance in terms of DC and analog/RF parameters. Further, to improve the high frequency performance of the device, Gaussian doping profile is considered in the drain region with different characteristic lengths which decreases the gate to drain capacitance and leads to drastic improvement in analog/RF figures of merit. Furthermore, the optimisation is performed with different concentrations for uniform and Gaussian drain doping profile and for various sectional length of lower work function of the gate electrode. Finally, the effect of temperature variation on the device performance is demonstrated.     

A 10-s doping technology for the application of low-temperaturepolysilicon TFTs to giant microelectronics

A bucket-type high-density (0.25-1.2-mA/cm²) low-energy (500-2000 V) ion source was utilized for high-speed phosphorus doping directly into a thin polysilicon layer without cap SiO₂. Doping gas with He dilution was selected to reduce etching of polysilicon film. Excimer laser (XeCl, 8 mm×8 mm) pulse annealing was introduced to activate effectively the doped impurity. The combination of these techniques provided a practically low sheet resistance for the TFT source, drain, and gate with a short time doping. The low-temperature polysilicon TFT fabricated with a doping time of 10 s had characteristics comparable to those of that fabricated by a longer time doping or conventional ion implantation, showing the practicality of this technology and its promise for giant microelectronics     

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A_VO) and cut-off frequency (f_T) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 μA/μm, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g_m), transconductance-to-current ratio (g_m/I_ds), Early voltage (V_EA), output conductance (g_ds) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs.     

A novel PMOS SOI polysilicon transistor

An advanced silicon-on-insulator (SOI) PMOS polysilicon transistor, featuring an inverted gate electrode and self-aligned source/drain and gate/channel regions, is developed and characterized. Selective oxidation is used to form self-aligned thin polysilicon channel regions with thicker source/drain polysilicon regions. The gate electrode is formed by a high-energy boron implant into the underlying silicon substrate. Since the gate oxide is formed over single-crystal silicon rather than polysilicon, an improvement in gate oxide integrity is possible. The resulting SOI PMOS device is suitable for high-density static random access memory (SRAM) circuit applications and exhibits excellent short-channel behavior with an on/off current ratio exceeding six orders of magnitude     

复合多晶硅栅LDMOS的设计

提出了一种应用于射频领域的复合多晶硅栅LDMOS结构,并提出了具体的工艺实现方法。此结构采用栅工程的概念,设计的栅由S-gate和D-gate两块并列组成,S-gate用高功函数P型多晶硅材料,D-gate用低功函数N型多晶硅材料。MEDICI模拟结果表明,该结构能够降低沟道末端和漏极附近的最高电场强度,提高器件的跨导和截止频率;同时,还能够提高器件的击穿电压,并减小器件的热载流子效应。     

Design of a novel double doping polysilicon gate MOSFET

In this paper, a novel design of the double doping polysilicon gate MOSFET device is proposed, which has a p+ buried layer near the drain, and relatively thicker D-gate oxide film (DDPGPD MOSFET). The detailed fabrication process for this device is designed using process simulation software called TSUPREM, and the device structure plan is further used in MEDICI simulation. The effect of gate doping concentration is investigated, and it is found that the device V_th is only influenced by the S-gate; furthermore, the device can get a larger driving current by increasing the doping concentration of D-gate. Compared to other conventional DDPG MOSFETs, the short-channel effects (SCEs) including the off-state current, the gate leakage current and the drain induced barrier lowering effect (DIBL) can be effectively suppressed by the p+ buried layer and thicker D-gate oxide film. Additionally, the other parameters of the device such as the driving current are not seriously affected by the proposed design modifications.     

A novel p-n junction polycrystalline silicon gate MOSFET†

A segmented multiple gate MOSFET utilizing a single level of polysilicon gate layer was fabricated and characterized. Data presented for both p- and n-channel devices in which the polysilicon gate layer is segmented into three separate lateral gates by alternate p- and n-typo doping. It was found that current conduction takes place from the source to the drain by applying appropriate potentials to the end gates oven though the central gate was left floating. The harrier potential of the diodes formed within the polysilicon gate layer was measured together with their threshold voltage which was found to be substantially different under the p- and n-type gates..It is concluded that this difference is only partially duo to the difference in work function of the two types of gates ; the rest is due to a difference in the effective surface state density Qss which was, as expected, always found to be positive. It was also found that for both p- and n-channel devices, the Qss was larger for n⁺ gate in comparison with the pH gate. Transfer characteristics of the device were also measured and modelled satisfactorily by applying the standard MOSFET theory suitably modified to account for the different threshold voltage of the p⁺ and n⁺ polygate. Based on this DC characterization, it is proposed that the device would be suitable for CCD or logic gates in which the single polysilicon gate layer could afford higher packing density and yield.     

Cobalt disilicide as dopant diffusion source for polysilicon gates in MOS devices

In this paper, a novel p-channel metal oxide semiconductor (PMOS) device fabrication process using BF₂-implanted CoSi₂ as a boron diffusion source for both polycrystalline-silicon (polysilicon) gate doping and shallow source/drain junction formation is studied. Important issues including thermal stability of the CoSi₂/polysilicon stacked layer and boron redistribution in the CoSi₂/polysilicon stacked layer are discussed in detail. The data show that the thermal stability of CoSi₂/polysilicon stacked layers can be significantly improved by using as-deposited amorphous silicon films rather than as-deposited polysilicon films. Samples with 120 nm CoSi₂ on 180 nm polysilicon are thermally stable up to 1000°C for 60 s in a N₂ ambient. Secondary ion mass spectroscopy analyses show that degenerately doped polysilicon gates and shallow source/drain junctions can be achieved simultaneously. Furthermore, a simple method to study the electrically active dopant redistribution in CoSi₂polysilicon gates using MOS capacitors is proposed.