双栅MOSFET高频特性的实验研究

设计制作了不同沟道长度、栅材料以及栅电极构形的各种双栅MOSFET。通过实验全面研究了设计和工艺参数对器件高频特性的影响,阐明了双栅MOSFET的高频设计思想,给出了全离子注入高频低噪声工艺。有效沟道长度为1μm的超高频双栅MOSFET在900MHz下功率增益为17dB,有效沟道长度为1.5μm的甚高频器件在200MHz下功率增益为23dB.     

垂直纳米线晶体管的制备技术

对目前垂直纳米线晶体管的制备技术进行了综述.首先根据器件结构取向介绍了纳米线晶体管的分类,即水平纳米线晶体管和垂直纳米线晶体管,比较了这两类不同结构晶体管的优缺点,阐述了垂直纳米线晶体管的优势及其潜在应用价值.重点介绍了两种主流的垂直纳米线晶体管的制造方法,即自下而上方法和自上而下方法,自上而下方法则又分为后栅工艺和先栅工艺.随后详细比较了它们之间的不同.最后,对垂直纳米线晶体管制造过程中的工艺挑战进行了分析,提出了几种可行的解决方案,并预测了垂直纳米线晶体管未来的发展趋势,特别是在低功耗器件及3D存储器等方面的发展走向.     

五氧化二钽高K薄膜作为MOSFET绝缘栅研究

本文综述了MOSFET栅介质的最新研究状况.介绍了Ta2O5高K薄膜材料作为MOSFET栅氧化物在现阶段主要的制备技术和进展.电学性能是今后研究应关注的主要方面.最后展望了其在MOSFET绝缘栅的研究前景.     

氮退火对SiC MOSFET栅源电压漂移的影响

为了准确地表征4H-SiC MOSFET经过高温栅偏(HTGB)测试后的栅源电压漂移,优化氮退火工艺条件以改善MOSFET栅源电压的稳定性,在n型4H-SiC (0001)外延片上制备了横向扩散MOSFET (LDMOSFET)和纵向扩散MOSFET (VDMOSFET).对栅氧化层采用不同温度、时间和气氛进行氮退火,并对制备的MOSFET进行了HTGB测试,探讨了栅压应力大小、应力时间、温度对栅源电压漂移的影响.结果 表明:相比LDMOSFET,VDMOSFET可以更有效地表征栅源电压漂移趋势;氮退火对栅源电压正向漂移影响较小;NO退火后增加高温N2退火、提高NO退火的温度和增加NO退火的时间均会引起VDMOSFET栅源电压负向漂移量增加;当栅压应力为-16 V、应力时间为500 s时,1200℃、70 min NO退火的VDMOSFET的栅源电压漂移比1250℃、40 min NO退火的小0.1～0.3 V.     

硅基Ⅲ-Ⅴ族纳米线晶体管

硅基Ⅲ-Ⅴ族纳米线晶体管已经成为高速、低功耗纳米级器件的重要发展方向。首先,从气相-液相-固相生长和选择区域生长的角度,阐明了在硅衬底上无位错生长高晶体质量Ⅲ-Ⅴ族纳米线的机制。在此基础上,介绍了垂直结构和水平结构Ⅲ-Ⅴ族纳米线晶体管的制备方法。研究表明,垂直结构纳米线容易实现高密度生长,而水平结构纳米线有利于逻辑栅的制作。通过比较垂直生长、水平生长、衬底转移和自上而下纳米加工技术制备Ⅲ-Ⅴ族纳米线的工艺优缺点,为水平结构Ⅲ-Ⅴ族纳米线在硅衬底上的大面积异构集成及其器件的制作提供了新的解决方案。     

一种基于双极工艺的纵向多面栅MOSFET的结构与工艺

提出了一种基于双极工艺的纵向多面栅MOSFET的结构和工艺。应用此项技术能够方便地形成双栅、三栅以及围栅等各种多面栅结构；同时，应用体迁移进行载流子传输的纵向结构能够显著地改善MOS器件的性能，立体结构更为三维集成提供了发展的基础。工艺模拟证明了该结构的可行性，文中还对实际生产中应注意的一些非理想情况进行了预测和分析。     

1200V大容量SiC MOSFET器件研制

采用平面栅MOSFET器件结构,结合优化终端场限环设计、栅极bus-bar设计、JFET注入设计以及栅氧工艺技术,基于自主碳化硅工艺加工平台,研制了1200V大容量SiC MOSFET器件.测试结果表明,器件栅极击穿电压大于55V,并且实现了较低的栅氧界面态密度.室温下,器件阈值电压为2.7V,单芯片电流输出能力达到50A,器件最大击穿电压达到1600V.在175℃下,器件阈值电压漂移量小于0.8V;栅极偏置20V下,泄漏电流小于45nA.研制器件显示出优良的电学特性,具备高温大电流SiC芯片领域的应用潜力.     

SnO_2纳米线基场效应晶体管的电学性能研究

基于气-液-固生长机理和原位掺杂技术,成功制备了2%(质量分数)Sb掺杂SnO_2纳米线,所制器件可以在低压环境下工作且不受栅漏电的影响;将该纳米线作为场效应晶体管的沟道,分析了不同比例的Sb掺杂对晶体管电学性能参数的影响。结果显示:Sb质量分数由0.5%增加到2.5%时,随着Sb掺杂量的增大,晶体管的稳定性增强,但栅电压的调控能力减弱,晶体管功耗增大且对空穴和电子的迁移能力减弱。     

一种高性能背栅三明治纳米线场效应晶体管器件的仿真研究

本文提出了一种新型背栅三明治纳米线场效应晶体管,结合了ETSOI和纳米线晶体管的优点,在保持良好的短沟道效应控制的基础上可以动态调节背栅电压的控制能力,其中背栅用于阈值电压的调节。和背栅FinFET相比,背栅三明治纳米线场效应晶体管具有更好的器件性能,在相同宽度的纳米线和Fin的条件下,三维器件仿真表明新型器件具有三倍的过驱动电流,减小75%的漏电流,并且具有更小的亚阈值摆幅和漏致势垒下降。本文还提出一种新的制作背栅三明治纳米线场效应晶体管的工艺流程和针对本器件的背栅电压调节阈值电压的解析模型,兼容于先进的高k金属栅CMOS技术,并且具有独特的背栅调控能力,有利于22纳米节点以下器件尺寸的减小。     

红外瞬态退火全离子注入MOS工艺的研究

研究了一种新的红外瞬态退火技术,其工艺与常规的MOS工艺高度兼容.本文报道了这种红外瞬态退火的全注入 MOS工艺.用这种工艺制备的1μm沟长的 MOSFET 的电性能良好。同时也制备了 3μm沟长的 23级环振器与沟长为2 μm的 43级环振器,这些环振器每级门的延迟时间分别是1ns和0.6ns.     

Fabrication of ultra-thin strained silicon on insulator

A bond and etch back technique for the fabrication of 13-nm-thick, strained silicon directly on insulator has been developed. The use of a double etch stop allows the transfer of a thin strained silicon layer with across-wafer thickness uniformity comparable to the as-grown epitaxial layers. Surface roughness of less than 1 nm was achieved. Raman analysis confirms strain remains in the thin silicon layers after the removal of the SiGe that induced the strain. Ultra-thin strained silicon-on-insulator (SSOI) substrates are promising for the fabrication of ultra-thin body and double-gate, strained Si metal-oxide semiconductor field-effect transistors (MOSFETs).     

An optimized junctionless GAA MOSFET design based on multi-objective computation for high-performance ultra-low power devices

An analytical investigation has been proposed to study the subthreshold behavior ofjunctionless gates all around （JLGAA） MOSFET for nanoscale CMOS analog applications. Based on 2-D analytical analysis, a new subthreshold swing model for short-channel JLGAA MOSFETs is developed. The analysis has been used to calculate the subthreshold swing and to compare the performance of the investigated design and conventional GAA MOSFET, where the comparison of device architectures shows that the JLGAA MOSFET exhibits a superior performance with respect to the conventional inversion-mode GAA MOSFET in terms of the fabrication process and electrical behavior in the subthreshold domain. The analytical models have been validated by 2-D numerical simulations. The proposed analytical models are used to formulate the objectives functions. The overall objective function is formulated by means of a weighted sum approach to search the optimal electrical and dimensional device parameters in order to obtain the better scaling capability and the electrical performance of the device for ultra-low power applications.     

Analog and radio-frequency performance analysis of silicon-nanotube MOSFETs

This work presents a comparative study of the influence of various parameters on the analog and RF properties of silicon-nanotube MOSFETs and nanowire-based gate-all-around (GAA) MOSFETs. The important analog and RF performance parameters of SiNT FETs and GAA MOSFETs, namely drain current (I_d), transconductance to drain current ratio (g_m/I_d), I_on/I_off, the cut-off frequency (f_T) and the maximum frequency of oscillation (f_MAX) are evaluated with the help of Y- and H-parameters which are obtained from a 3-D device simulator, ATLAS^TM. It is found that the silicon-nanotube MOSFETs have far more superior analog and RF characteristics (g_m/I_d, f_T and f_MAX) compared to the nanowire-based gate-all-around GAA MOSFETs. The silicon-nanotube MOSFET shows an improvement of~2.5 and 3 times in the case of f_T and f_MAX values respectively compared with the nanowire-based gate-all-around (GAA) MOSFET.     

SOI MOSFET器件的热载流子退化机理

介绍了绝缭体上硅（SOI）材料的制作方法．阐进了SOIMOSFET器件的热载流子注入效应的失效机理。研究表明：前沟和背面缺陷的耦合效应是SOI器件的特有现象．对SOI器件的退化构成潜在的威胁。虽然失效机理比体硅器件复杂,但并不会阻碍高性能、低电压ULSI SOI电路的发展。     

Analytical analysis of nanoscale multiple gate MOSFETs including effects of hot-carrier induced interface charges

As the channel length rapidly shrinks down to the nanoscale regime, the multiple gate MOSFETs structures have been considered as potential candidates for a CMOS device scaling due to its good short-channel-effects (SCEs) immunity. Therefore, in this work we investigate the scaling capability of Double Gate (DG) and Gate All Around (GAA) MOSFETs using an analytical analysis of the two dimensional Poisson equation in which the hot-carrier induced interface charge effects have been considered. Basing on this analysis, we have found that the degradation becomes more important when the channel length gets shorter, and the minimum surface potential position is affected by the hot-carrier induced localized interface charge density. Using this analysis, we have studied the scaling limits of DG and GAA MOSFETs and compared their performances including the hot-carrier effects. Our obtained results showed that the analytical analysis is in close agreement with the 2-D numerical simulation over a wide range of devices parameters. The proposed analytical approach may provide a theoretical basis and physical insights for multiple gate MOSFETs design including the hot-carrier degradation effects.     

A physical compact DC drain current model for long-channel undoped ultra-thin body (UTB) SOI and asymmetric double-gate (DG) MOSFETs with independent gate operation

In this paper, a new compact charge based DC model for the drain current of long channel fully depleted ultra-thin body SOI MOSFETs and asymmetric double-gate MOSFETs with independent gate operation (ADGMOSFETs) is presented. The model was validated by both TCAD simulations and electrical measurements with a good agreement. In particular, great care was taken during the derivation of the model in order to respect the physics of the device and to make the correct approximations. The obtained solutions can be viewed as a generalization of classical MOS theory to the case of undoped fully depleted ADGMOS. As a result, the model consists of relatively simple equations and is a promising approach for the compact modeling and parameter extraction of fully depleted SOI transistors.     

Impact of elliptical cross-section on the propagation delay of multi-channel gate-all-around MOSFET based inverters

Multi-channel (MC) gate-all-around (GAA) metal-oxide-semiconductor field-effect transistor (MOSFET) is one of the promising candidates for the next-generation high performance devices. However, due to fabrication imperfections the cross-section of GAA devices may be ellipse-shaped having different major (a) and minor (b) axes, instead of the theoretically ideal round shape. The aspect ratio (AR), defined as a/b, of such elliptical GAA devices can vary depending on a and b. This introduces variability in the effective diameter, which in turn affect the performance parameters of circuits based on elliptical GAA MOSFETs. In the present work we have investigated the impact of diameter variability on the transient response of MC elliptical GAA MOSFET based CMOS inverters with a novel perspective. We have modeled the spread in the effective diameter by a parameter, σ, the standard deviation (SD), which may be thought of as a quantitative measure of the amount of variability introduced in the device. We have elaborated the ‘ON-Resistance’ method for calculating the propagation delay of MC GAA MOSFET based CMOS inverters. Computations were carried out to show the dependence of the propagation delay of such inverters on some important device/circuit parameters. We have also shown that even long channel elliptical devices can offer significant reduction of circuit delay (comparable to short channel devices) by proper tuning the effective diameter and number of channels, provided the admissible small dimensional effects have been taken into account.     

SOI反偏肖特基势垒动态阈值MOS特性

将Ti硅化物-p型体区形成的反偏肖特基势垒结构引入绝缘体上硅动态阈值晶体管.传统栅体直接连接DTMOS,为了避免体源二极管的正向开启,工作电压应当低于0.7V.而采用反偏肖特基势垒结构,DTMOS的工作电压可以拓展到0.7V以上.实验结果显示,室温下采用反偏肖特基势垒SOI DTMOS结构,阈值电压可以动态减小200mV.反偏肖特基势垒SOI DTMOS结构相比于传统模式,显示出优秀的亚阈值特性和电流驱动能力.另外,对浮体SOI器件、传统模式SOI器件和反偏肖特基势垒SOI DTMOS的关态击穿特性进行了比较.     

SOI反偏肖特基势垒动态阈值MOS特性

将Ti硅化物-p型体区形成的反偏肖特基势垒结构引入绝缘体上硅动态阈值晶体管.传统栅体直接连接DTMOS,为了避免体源二极管的正向开启,工作电压应当低于0.7V.而采用反偏肖特基势垒结构,DTMOS的工作电压可以拓展到0.7V以上.实验结果显示,室温下采用反偏肖特基势垒SOI DTMOS结构,阈值电压可以动态减小200mV.反偏肖特基势垒SOI DTMOS结构相比于传统模式,显示出优秀的亚阈值特性和电流驱动能力.另外,对浮体SOI器件、传统模式SOI器件和反偏肖特基势垒SOI DTMOS的关态击穿特性进行了比较.     

薄膜SOI材料MOSFET的高温泄漏电流

在对体硅MOSFET高温泄漏电流研究的基础上,深入研究了SOI材料MOSFET泄漏电流的组成、解析式及高温模拟结果,并与体硅MOSFET进行了比较,证明薄膜SOI材料MOSFET的高温泄漏电流明显减小,因而在高温领域中有着广阔的应用前景。