可用于高密度高速度领域的一种新型两端静态存储单元的设计

A vertical two-terminal silicon PNPN diode is presented for use in a high-density memory cell. The device design for high-speed operations was studied with experiments and calibrated simulations, which proves that the proposed memory cell can be operated at nanosecond range. The static and dynamic power dissipations were also studied, which indicated the availability of the proposed memory cell for VLS1 applications. Moreover, the memory cell is compatible with CMOS process, has little impact from process variation, and has good reliability.     

应用于三维集成的晶圆级键合技术

随着芯片集成度的不断提高以及CMOS工艺复杂度的增加,集成电路的成本及性能方面的问题越来越突出,基于TSV技术的三维集成已成为研究热点,并很有可能是未来集成电路发展的方向.在三维集成中,键合技术为芯片堆叠提供电学连接和机械支撑,从而实现两层或多层芯片间电路的垂直互连.介绍了几种晶圆级三维集成键合技术的特点及研究现状.     

TiN/TaN 厚度变化对nMOSCAP栅叠层有效功函数的影响

We evaluated the TiN/TaN/TiA1 triple-layer to modulate the effective work function （EWF） of a metal gate stack for the n-type metal-oxide-semiconductor （NMOS） devices application by varying the TiN/TaN thickness. In this paper, the effective work function of EWF ranges from 4.22 to 4.56 eV with different thicknesses of TiN and TaN. The thinner TiN and/or thinner in situ TaN capping, the closer to conduction band of silicon the EWF is, which is appropriate for 2-D planar NMOS. Mid-gap work function behavior is observed with thicker TiN, thicker in situ TaN capping, indicating a strong potential candidate of metal gate material for replacement gate processed three-dimensional devices such as FIN shaped field effect transistors. The physical understandings of the sensitivity of EWF to TiN and TaN thickness are proposed. The thicker TiN prevents the A1 diffusion then induces the EWF to shift to mid-gap. However, the TaN plays a different role in effective work function tuning from TiN, due to the Ta-O dipoles formed at the interface between the metal gate and the high-k layer.     

使用非对称内表面氧化层的MOS管性能优化

提出了一种用来提高短沟道MOS管性能的非对称内表面氧化层结构。该结构是在MOS管的源端附近生长一层厚的内表面氧化层,以抑制载流子迁移率的降低,同时,在MOS管的漏端附近生长一层薄的内表面氧化层,以抑制器件的短沟道效应。使用TCAD软件进行仿真和分析,结果显示,与对称内表面氧化层结构相比,非对称内表面氧化层结构具有更好的导通-关断特性。对器件进行优化,当源端较厚的内表面氧化层占总氧化层的比例为15%左右时,器件的性能得到最大幅度的提高。在相同的关断电流下,与对称内表面氧化层器件相比,非对称内表面氧化层器件的导通电流提高5%~15%。     

使用非对称内表面氧化层的MOS管性能优化

提出了一种用来提高短沟道MOS管性能的非对称内表面氧化层结构。该结构是在MOS管的源端附近生长一层厚的内表面氧化层,以抑制载流子迁移率的降低,同时,在MOS管的漏端附近生长一层薄的内表面氧化层,以抑制器件的短沟道效应。使用TCAD软件进行仿真和分析,结果显示,与对称内表面氧化层结构相比,非对称内表面氧化层结构具有更好的导通-关断特性。对器件进行优化,当源端较厚的内表面氧化层占总氧化层的比例为15%左右时,器件的性能得到最大幅度的提高。在相同的关断电流下,与对称内表面氧化层器件相比,非对称内表面氧化层器件的导通电流提高5%~15%。     

关于超薄埋氧层及超薄SOI的MOSFET器件衬底掺杂的设计研究

The importance of substrate doping engineering for extremely thin SOI MOSFETs with ultra-thin buried oxide(ES-UB-MOSFETs) is demonstrated by simulation.A new substrate/backgate doping engineering,lateral non-uniform dopant distributions(LNDD) is investigated in ES-UB-MOSFETs.The effects of LNDD on device performance,V t-roll-off,channel mobility and random dopant fluctuation(RDF) are studied and optimized.Fixing the long channel threshold voltage(V t) at 0.3 V,ES-UB-MOSFETs with lateral uniform doping in the substrate and forward back bias can scale only to 35 nm,meanwhile LNDD enables ES-UB-MOSFETs to scale to a 20 nm gate length,which is 43% smaller.The LNDD degradation is 10% of the carrier mobility both for n MOS and p MOS,but it is canceled out by a good short channel effect controlled by the LNDD.Fixing V t at 0.3 V,in long channel devices,due to more channel doping concentration for the LNDD technique,the RDF in LNDD controlled ES-UB-MOSFETs is worse than in back-bias controlled ES-UB-MOSFETs,but in the short channel,the RDF for LNDD controlled ES-UB-MOSFET is better due to its self-adaption of substrate doping engineering by using a fixed thickness inner-spacer.A novel process flow to form LNDD is proposed and simulated.     

具有夹层的垂直U型栅极TFET的设计

通过使用工艺计算机辅助设计(TCAD)仿真技术提出了一种新型的带有夹层的垂直U型栅极隧穿场效应晶体管(TFET)结构.该器件是通过优化基于Ge的栅极金属核垂直纳米线TFET结构获得的.通过在沟道中增加重掺杂夹层,器件的平均亚阈值摆幅(SSavg)得到了改善;又通过改变器件的源极和漏极材料,器件的开关电流比(Ion/Ioff)得到了改善.对夹层的掺杂浓度和厚度以及沟道的高度也进行了优化.最终优化后的器件开态电流为220 μA/μm,关态电流为3.08×10-10μA/pm,SSavg为8.6 mV/dec,表现出了优越的性能.与初始器件相比,该器件的SSavg减小了 77％,Ion/Ioff增加了两个数量级以上.此外,提出了针对该器件的可行的制备工艺步骤.因此,认为该器件是在超低功耗应用中非常具有潜力的候选器件.     

亚20nm节点后栅工艺体硅FinFET器件参数优化研究

文章研究了亚 20nm 节点后栅工艺体硅 FinFET PMOS 器件制作过程中一系列工艺参数对器件微缩的影响。实验结果表明细且陡的梯形Fin结构有更好的性能。文章针对穿通阻挡层（PTSL） 和轻掺杂源漏扩散区 （SDE）的注入条件也进行了仔细地优化。SDE之后没有热退火过程的器件由于在源漏退火之后有更好的晶格再生因而拥有更大的驱动电流。带边功函数器件能够改善短沟道效应,而带中功函数具有更大的驱动电流。器件在微缩过程中针对金属栅的有效功函数需要折衷选择。     

石墨烯背栅器件在空气中稳定性的研究

The stability of a graphene field effect transistor(GFET) is important to its performance optimization, and study of hysteresis behavior can propose useful suggestions for GFET fabrication and optimization.In this work,a back-gate GFET has been fabricated and characterized,which is compatible with the CMOS process.The stability of a GFET in air has been studied and it is found that a GFET’s electrical performance dramatically changes when exposed to air.The hysteresis characteristic of a GFET depending on time has been observed and analyzed systematically.Hysteresis behavior is reversed at room temperature with the Dirac point positive shifted when the GFET is exposed to air after annealing.     

Top-TiN生长条件及TaN厚度对MOSCAP栅叠层有效功函数的影响

我们引入TaN/TiAl/top-TiN三层结构,通过变化TaN的厚度及top-TiN的生长条件来调节TiN-based金属栅叠层的有效功函数。实验结果显示：较薄的TaN和PVD-process生长的top-TiN组合可以得到较小的有效功函数(EWF),而较厚的TaN和ALD-process生长的top-TiN组合可以得到较大的有效功函数(EWF),文中EWF有从4.25eV to 4.56eV的变化。同时文中也给出了TaN厚度及top-TiN的生长条件调节有效功函数(EWF)的物理解释。与PVD-process在室温条件下生长TiN相比,ALD-process TiN是在400 ℃条件下生长的,400 ℃ ALD-process TiN 可以为整个工艺过程提供更多的热预算,从而促进更多的Al原子扩散进入top-TiN,导致扩散进入到bottom-TiN的Al原子数量减少。另外,厚的TaN也会阻止Al原子进入bottom-TiN。这些因素都减少了bottom-TiN中Al原子的数量,减弱了Al原子对有效功函数的调节作用,从而引起EWF的增加。