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随着SoC的复杂度和规模的不断增长,SoC的片上调试与可测性变得越来越困难和重要。片上调试与可测性都是系统芯片设计的重要组成部分。文章针对某款32位SoC,充分利用CPU核原有的调试结构,提出一种可测试系统与调试系统的一体化结构设计,并针对不同的模块利用不同的测试策略。基于JTAG端口,该结构能够进行系统程序的调试、边界扫描的测试、扫描链的测试、嵌入式SRAM的内建自测试,同时有效地降低了电路逻辑规模,实现了在测试覆盖率和测试代价之间的一个有效折衷。 相似文献
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LSC87中嵌入式ROM内建自测试实现 总被引:2,自引:1,他引:1
LSC87芯片是与Intel8086配套使用的数值协处理器,体系结构复杂,有较大容量的嵌入式ROM存储器,考虑到与Intel8087的兼容性和管脚的限制,必须选择合适的可测性设计来提高芯片的可测性。文章研究了LSC87芯片中嵌入式ROM存储器电路的设计实现,然后提出了芯片中嵌入式ROM电路的内建自测试,着重介绍了内建自测试的设计与实现,并分析了采用内建自测试的误判概率,研究结果表明,文章进行的嵌入式ROM内建自测试仅仅增加了很少的芯片面积开销,获得了满意的故障覆盖率,大大提高了整个芯片的可测性。 相似文献
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随着集成电路技术的发展,可测性设计在电路设计中占有越来越重要的地位,内建自测试作为可测性设计的一种重要方法也越来越受到关注。文中首先介绍了内建自测试的实现原理,在此基础上以八位行波进位加法器为例,详细介绍了组合电路内建自测试的设计过程。采用自顶向下的设计方法对整个内建自测试电路进行模块划分,用VHDL语言对各个模块进行代码编写并在QuartusII软件环境下通过了综合仿真,结果表明此设计合理,对电路的测试快速有效。 相似文献
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系统芯片的可测性设计与测试 总被引:2,自引:0,他引:2
阐述了系统芯片(SoC)测试相比传统IC测试的困难,SoC可测性设计与测试结构模型,包括测试存取配置、芯核外测试层,以及测试激励源与测试响应汇聚及其配置特性、实现方法与学术研究进展,介绍了基于可复用内嵌芯核的SoC国际测试标准IEEE P1500的相关规约;最后,建议了在SoC可测性设计及测试中需要密切关注的几个理论问题。 相似文献
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在设计基于IP模块的SoC同时,必须引入可测性设计以解决SoC的测试问题.为了简化SoC中的可测性设计的工作,本文设计了一种新型测试结构复用技术,通过分析SoC内部的各种测试应用情况,实现了一个兼容IEEE1149.1标准的通用测试访问逻辑IP.在运动视觉SoC中的应用以及仿真结果验证了这种测试复用结构的有效性,并有助于提高SoC的测试覆盖率. 相似文献
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介绍了几种主要的VLSI可测性设计技术,如内部扫描法、内建自测试法和边界扫描法等,论述如何综合利用这些方法解决SOC内数字逻辑模块、微处理器、存储器、模拟模块、第三方IP核等的测试问题,并对SOC的可测性设计策略进行了探讨. 相似文献
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IP核可测试性架构的多样性、互不兼容性给SoC的测试带来不便,IEEE Std1500针对此问题提出了一种标准的、可配置的可测试性架构,如何设计实现这种架构便成为SoC测试研究的热点问题.基于IEEE Std1500,利用边界扫描技术,结合自行设计的IP核,本文给出标准化架构的设计过程,利用quartus ii平台仿真验证了多种测试指令下设计的有效性.提出的外壳并行配置设计打破传统串行测试的局限性,为实现SoC中IP核的并行测试、缩短测试时间提供新的思路. 相似文献
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Mouna Karmani Chiraz Khedhiri Belgacem Hamdi Ka Lok Man Rached Tourki 《International Journal of Electronics》2013,100(6):837-850
Dependability requirements must be considered from the beginning when designing safety-critical systems. Therefore, testing should even be considered earlier, intertwined with the design process. The process of designing for better testability is called design for testability (DfT). This article presents two designs for testability and fault diagnosis techniques using a new design analogue checker circuit in order to improve the testability and the diagnosability of nano-CMOS (complementary metal oxide semiconductor) analogue circuits used in safety-critical applications based on the system-on-chip (SoC) approach design. The testing techniques presented in this work can be done during and after the system fabrication. The checker is implemented in full-custom 65 nm Complementary metal–oxide–semiconductor (CMOS) technology with low supply voltage and small-size capabilities. SPICE simulations of the post-layout extracted CMOS checker, which include all parasitic, are used to validate the technique and demonstrate the acceptable electrical behaviour of the checker. 相似文献
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This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock. 相似文献
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Built-in self-test (BIST) has emerged as a promising test solution for high-speed, deep sub-micron VLSI circuits. Traditionally, the testability insertion phase comes after functional logic synthesis and verification in the design cycle. This creates two separate optimisation processes: functional optimisation followed by BIST insertion and optimisation. The first deals with functional design behaviour, while the second deals with test behaviour. Considering testability at such a late stage in the design flow limits efficient design space exploration. In this paper, we consider testability as a design objective alongside area and delay. We extend the concept of design space to include testability and show how this enhanced design space can be used by a high-level synthesis tool. We demonstrate that by taking testability into account at an early stage, we can generate better designs than by leaving BIST insertion to the end of the design cycle. 相似文献
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Bombana M. Buonanno G. Cavalloro P. Ferrandi F. Sciuto D. Zaza G. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1994,2(2):157-171
In order to cope with tomorrow's challenges in the microelectronic market, the reliability of the first phases of the design process must be improved. The possibility of applying techniques for testability analysis at these abstract design levels can considerably help in achieving this goal, reducing at the same time system design costs. In this paper we introduce a novel approach for the application of functional testability at system design level and demonstrate the possibility of its application in an industrial environment. Testability conditions referring to both regular and irregular topologies have been defined, formalized and inserted into the knowledge base of the expert system, ALADIN. This tool operates as a testability analyzer able to identify critical areas for testability in designs whose functional modules and local interconnections are known and described in standard VHDL. The architecture of the tool has been defined in order to satisfy the users' requirements including the integrability into a standard CAD design flow through standard I/O interfaces. Then its application to both a regular and an irregular topology are presented in order to show on real examples which testability conditions apply, and how the tool operates in order to reach the testability assessment. From these industrial case studies, figures of merit are derived from which it is possible to evaluate the importance of the application of such a methodology to system level design 相似文献
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UML for electronic systems design: a comprehensive overview 总被引:2,自引:0,他引:2
Yves Vanderperren Wolfgang Mueller Wim Dehaene 《Design Automation for Embedded Systems》2008,12(4):261-292
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This paper proposes a new automatic compensation network (ACN) for a system‐on‐chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on‐chip ACN using 0.18 µm SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design‐for‐testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment. 相似文献