多带激励低速率语音压缩编码算法研究及实时实现

本文以多带激励声码器为模型，采用了多种技术去降低编码速率和改善音质，我们利用动态规划算法对基音周期进行了平滑，去除了声码器中常用的音调噪声，ＭＢＥ算法对谱包络的量化要花费大量的比特，这里利用ＬＰＣ全极点模型谱逼近ＭＢＥ谱包络，并采用共振峰增强技术来补偿模型误差，对谱幅度参数的量化，采用了分裂矢量量化（ＳＰＶＱ）和多级矢量量化（ＭＳＶＱ）的方法，使之在２．４ｋｂｐｓ，１．２ｋｂｐｓ及８００ｂｐｓ等速     

二维DWT／IDWT处理器的VLSI设计

在本文中，我们设计了基于多分辨分析，适合于硬件实现的二维ＤＷＴ和ＩＤＷＴ实时系统，采用了ｔｏｐ－ｄｏｗｎ的ＶＬＳＩ设计方法，用硬件描述语言ＶＨＤＬ，在Ｓｙｎｏｐｓｙｓ系统中进行了验证和综合，综合结果表明：系统的规模为７１４０单元面积，对于四层信小波变换，数据处理速度约可达到４Ｍｐｉｘｅｌ／ｓ。     

基于DCT子空间失真测度的矢量量化VLSI结构设计

本文提出了一种实现离散余弦变换子空间失真测度矢量编码算法的ＶＬＳＩ结构。     

高速Viterbi处理器—流水式块处理并行结构

本文提出一种流水式块处理并行Ｖｉｔｅｒｂｉ处理器，可以得到ＬＭ倍增速（Ｍ为流水级数，Ｌ为块长度），为达到更高速的Ｖｉｔｅｒｂｉ处理器提供了新型的并行结构。它可用Ｓｙｓｔｏｌｉｅ阵列构成，因而适于ＶＬＳＩ实现。     

采用Systolic阵列作为自适应波束形成的最佳权值提出取器

本文介绍了用于多旁瓣对消器（ＭＳＣ）和最小协方差不失真响应（ＭＶＤＲ）波束形成器的并行及全传送瞬时最佳权值提取中所采用的Ｓｙｓｔｏｌｉｃ算法和结构。所提出的Ｓｙｓｔｏｌｉｃ平行四边形阵列处理器是并行且全传送的，并且可以在无需正向和逆向替代的情况下瞬时地提取最佳权值。我们还指出，采用无平方根的Ｇｉｖｅｎｓ方法来改进通过速率并提高系统速度是很容易做到的。因此，这些ＭＳＣ和ＭＶＤＲＳｖｓｔｏｌｉｃ阵列权值提取系统对于在现实的雷达或声纳系统中实现实时的超大规模集成电路（ＶＬＳＩ）是十分合适的。     

宽带接入网的新发展

通信业务正在飞跃发展,除了传统的电话业务,各种宽带通信业务如电视会议、可视电话、远程医疗、远程教学、远程数字监控等如雨后春笋般大量涌现,对接入网提出了新要求。 ＶＤＳＬ是可提供比ＡＤＳＬ更高码率但仍利用普通电话线的一种宽带接入网,其下行码率高达１３～２６Ｍｂｉｔ／ｓ,传输距离不超过３００米。 ＵＡＤＳＬ则是另一种ＡＤＳＬ,其码率低于普通的ＡＤＳＬ,数码率降为１．５４４Ｍｂｉｔ／ｓ,但已可满足宽带通信初期发展的需要,而且可广泛利用现有的绝大部分普通电话线。 ＬＭＤＳ是近年开发的利用微波的宽带本地多点分配服务系统,工作在２８ＧＨｚ频段,数码率高达１５５Ｍｂｉｔ／ｓ,小区覆盖半径３～５ｋｍ,采用视线（ＬＯＳ）传输方式,一个节点可提供８万个数据和电话服务,有“无线光缆”之称。 ＡＰＯＮ（ＡＴＭ－ＰＯＮ）是一种利用无源光网络的宽带接入网,是近年来ＩＴＵ—Ｔ刚推出的新型接入网,其优点是带宽足够宽、ＱｏＳ可保证、性能稳定,是光纤到户的接入方式,将来应用十分广泛。 下面主要讨论ＶＤＳＬ、ＵＡＤＳＬ,也介绍一些有关 ＬＭＤＳ和 ＡＰＯＮ的应用和技术。 ＶＤＳＬ 一、ＶＤＳＬ系统和应用 ＶＤＳＬ（Ｖｅｒｙ ｈｉｇｈ ｓｐｅｅｄ ...     

一种电流型10位D／A转换器的设计

介绍了一种电流型１０位Ｄ／Ａ转换器的设计。着重阐述了差分式电流开关，Ｒ－２Ｒ梯形电阻、二进制电流加权网络和精密基准源的设计原理和结构。该Ｄ／Ａ转换器采用线性兼容Ｉ２Ｌ工艺制作，具有体积小、功耗低、可靠性高、使用方便灵活等特点。线性误差、微分线性误差均低于１／２ＬＳＢ，建立时间≤２００ｎｓ，在－１５Ｖ电源下功耗低于６０ｍＶ。     

Stepper领域的欧洲劲旅——ASML公司

Ｓｔｅｐｐｅｒ领域的欧洲劲旅———ＡＳＭＬ公司荷兰的ＡＳＭＬ光刻设备公司，创建于１９８４年，其前身为最早（１９７３年）在世界上设计、开发了第一台片子步进机（Ｓｔｅｐｐｅｒ）雏形的荷兰Ｐｈｉｌｉｐｓ公司。它是一家主要致力于ＶＬＳＩ和ＵＬＳＩ电路制造的光...     

一种应用于旁瓣对消系统的MGS算法

本文论述相控阵雷达的一种自适应波束形成算法，分析了基于Ｓｙｓｔｏｌｉｃ结构的ＳＬＣ系统的ＭＧＳ算法，分析和计算机模拟结果表明，在ＳＬＣ系统中ＭＧＳ算法在抑制干扰方面是有效的。     

在系统可编程技术在硬件设计中的应用

ＩＳＰ（在系统可编程）技术在ＣＭＯＳ ＰＬＤ领域中处于领先地位。ＩＳＰ器件能完成很多的系统性能,所有的器件能够通过一个简单的菊花链结构进行编程,并利用下载电缆将熔丝件写入ＩＳＰ器件。在熟悉ＩＳＰ ＰＬＤ技术的工作原理和ＶＨＤＬ环境并掌握ＩＳＰ开发工具（包括ＷＶＯｆｆｉｃｅ与ｉｓｐＤＳ＋５．０）情况下,利用ＶＨＤＬ将该技术应用到ＭＣＵ硬件的设计,并根据芯片的管脚锁定,利用ＰＲＯＴＥＬ制成一块ＰＣＢ     

VLSI电路划分问题的分散搜索算法

电路划分是超大规模集成电路(VLSI)设计自动化中的一个关键阶段,是NP困难的组合优化问题.本文把基于顶点移动的Fiduccia-Mattheyses(FM)算法结合到分散搜索算法框架中,提出了电路划分的分散搜索算法.算法利用FM算法进行局部搜索,利用分散搜索的策略进行全局搜索.为满足该方法对初始解的质量和多样性的要求,采用贪心随机自适应搜索过程(GRASP)和聚类相结合的方法产生初始解.实验结果表明,算法可以求解较大规模的电路划分实例,且与基于多级框架的划分算法hMetis相比,划分的质量有明显的提高.     

A versatile data string-search VLSI

A versatile data string-search VLSI has been fabricated using 1.6-μm CMOS technology. The VLSI consists of an 8 K content addressable memory (CAM) and a 20 K-gate finite-state automation logic (FSAL). A number of unique functions, such as strict/approximate-match string search and fixed/variable-length `don't care' operations, were implemented. A total of 217600 transistors have been integrated on an 8.62×12.76-mm die. The unique functions were efficiency tested by the scan path method. The data comparison rate was 5.12 billion characters/s in text-search application     

一种新的基于遗传算法的快速运动估计方法

本文提出了一种新的基于遗传算法的快速运动估计方法.该方法对遗传算法进行了改进,采用"阈值法"确定选择算子,并将基因变异所导致的随机搜索与特定目标搜索相结合,解决了以往快速搜索算法易陷于局部最优的问题,大大提高了运动估计速度.该方法还将运动矢量空间一致性原则用于初始种群的选取,进一步提高了算法性能.由于其具备遗传算法固有的规则性和高度并行性,该方法适合于采用VLSI实现实时视频编码器.     

Multiplierless Implementations of MF/DTMF Receivers

The ever-increasing use of VLSI in telecommunications systems is leavening the search of new algorithms for task realizations suited to VLSI implementations of systems. Toward this search, the paper presents implementations for MF/DTMF receivers, which are based on multiplierless basic filters or primitive VLSI cells such as(1 + z^{-n}),(1 - z^{-n}), and(1 pm z^{-n} + z^{-2n}). These implementations require parallel processing and are designed to meet the requirements of a switching system.     

基于神经网络的片上互连线电感提取法

通过将具有自学习能力和记忆功能的神经网络应用于平行导体间的电感计算，结合移动窗口方法搜索作用域，实现片上互连寄生电感参数提取。仿真例子表明，此方法能够快速、有效地实现电感提取，可作为VLSI互连线性能分析、设计的有效向导。     

Hybrid genetic-paired-permutation algorithm for improved VLSI placement

This paper addresses Very large-scale integration (VLSI) placement optimization, which is important because of the rapid development of VLSI design technologies. The goal of this study is to develop a hybrid algorithm for VLSI placement. The proposed algorithm includes a sequential combination of a genetic algorithm and an evolutionary algorithm. It is commonly known that local search algorithms, such as random forest, hill climbing, and variable neighborhoods, can be effectively applied to NP-hard problem-solving. They provide improved solutions, which are obtained after a global search. The scientific novelty of this research is based on the development of systems, principles, and methods for creating a hybrid (combined) placement algorithm. The principal difference in the proposed algorithm is that it obtains a set of alternative solutions in parallel and then selects the best one. Nonstandard genetic operators, based on problem knowledge, are used in the proposed algorithm. An investigational study shows an objective-function improvement of 13%. The time complexity of the hybrid placement algorithm is O(N²).     

Cost Effective VLSI Architectures for Full-Search Block-Matching Motion Estimation Algorithm

In this paper, we present efficient VLSI architectures for full-search block-matching motion estimation (BMME) algorithm. Given a search range, we partition it into sub-search arrays called tiles. By fully exploiting data dependency within a tile, efficient VLSI architectures can be obtained. Using the proposed VLSI architectures, all the block-matchings in a tile can be processed in parallel. All the tiles within a search range can be processed serially or concurrently depending on various requirements. With the consideration of processing speed, hardware cost, and I/O bandwidth, the optimal tile size for a specific video application is analyzed. By partitioning a search range into tiles with appropriate size, flexible VLSI designs with different throughput can be obtained. In this way, cost effective VLSI designs for a wide range of video applications, from H.261 to HDTV, can be achieved.     

一种低资源消耗的运动估计VLSI实现算法

现有的VLSI(verylarge scale integration)视频编码芯片多使用全搜索运动估计(ME)方法,且没有搜索中心偏移(CB)的并行实现方法。本文提出一种适合VLSI的H.264、AVS CB并行搜索方案,减少搜索点数量,降低逻辑资源的消耗,并且使用预测高概率区域的方法,保证ME精度。实验表明,本方法具备较好的率失真性能。在现场可编程门阵列(FPGA)平台上实现了本算法,逻辑综合的数据表明,硬件资源消耗降低了64%。本算法可应用于标清和高清电视(HDTV,hign-definition television)视频编码器。     

A fast block-matching algorithm based on adaptive search area and its VLSI architecture for H.264/AVC

In this paper, we propose a fast block-matching algorithm based on search center prediction and search early termination, called center-prediction and early-termination based motion search algorithm (CPETS). The CPETS satisfies high performance and efficient VLSI implementation. It makes use of the spatial and temporal correlation in motion vector (MV) fields and feature of all-zero blocks to accelerate the searching process. This paper describes the CPETS with three levels. At the coarsest level, which happens when center prediction fails, the search area is defined to enclose all original search range. At the middle level, the search area is defined as a 7×7-pels square area around the predicted center. At the finest level, a 5×5-pels search area around the predicted center is adopted. At each level, 9-points uniformly allocated search pattern is adopted. The experiment results show that the CPETS is able to achieve a reduction of 95.67% encoding time in average compared with full-search scheme, with a negligible peak signal-noise ratio (PSNR) loss and bitrate increase. Also, the efficiency of CPETS outperforms some popular fast algorithms such as: three-step search, new three-step search, four-step search evidently. This paper also describes an efficient four-way pipelined VLSI architecture based on the CPETS for H.264/AVC coding. The proposed architecture divides current block and search area into four sub-regions, respectively, with 4:1 sub-sampling and processes them in parallel. Also, each sub-region is processed by a pipelined structure to ensure the search for nine candidate points is performed simultaneously. By adopting search early-termination strategy, the architecture can compute one MV for 16×16 block in 81 clock cycles in the best case and 901 clock cycles in the poorest case. The architecture has been designed and simulated with VHDL language. Simulation results show that the proposed architecture achieves a high performance for real-time motion estimation. Only 47.3 K gates and 1624×8 bits on-chip RAM are needed for a search range of (−15, +15) with three reference frames and four candidate block modes by using 36 processing elements.     

A delay-encoding-logic array processor for dynamic-programming matching of data sequences

Computationally very expensive dynamic-programming matching of data sequences has been directly implemented in a fully-parallel-architecture VLSI chip. The circuit operates as digital logic in the signal domain, while analog processing is carried out in the time domain based on the delay-encoding-logic scheme. As a result, a high-speed low-power best-match-sequence search has been established with a small chip area. The typical matching time of 80 ns with the power dissipation of 2 mW has been demonstrated with fabricated prototype chips.