A New CMOS Image Sensor with a High Fill Factor and the Dynamic Digital Double Sampling Technique

介绍了基于0.35μm工艺设计的单片CMOS图像传感器芯片.该芯片采用有源像素结构,像素单元填充因数可达到43%,高于通常APS结构像素单元30%的指标.此外还设计了一种数字动态双采样技术,相对于传统的双采样技术(固定模式噪声约为0.5%),数字动态双采样技术具有更简洁的电路结构和更好抑制FPN噪声的效果.传感器芯片通过MPW计划采用Chartered 0.35μm数模混合工艺实现.实验结果表明芯片工作良好,图像固定模式噪声约为0.17%.     

CMOS图像传感器固定模式噪声抑制新技术。

针对有源像素(APS)CMOS图像传感器中的固定模式噪声(FPN),设计了一种动态数字双采样的噪声抑制新技术;该技术比普通双采样技术具有更佳的抑制效果,其电路结构简单,适合于像素尺寸不断缩小的CMOS图像传感器发展趋势。通过MPW计划,采用Chartered0.35μmCMOS工艺制作了测试ASIC芯片,试验结果表明动态数字双采样技术有效抑制了FPN噪声。     

基于0.35 μm工艺设计的APS CMOS图像传感器

介绍了一种基于CHRT公司0.35 μm工艺而设计的CMOS图像传感器.该图像传感器采用APS像素结构,像素阵列256×256,包含有列放大器、阵列扫描、串行接口、控制逻辑和ADC等模块.该图像传感器采用动态数字双采样(DDDS)的新方法消除FPN噪音,并已经通过MPW采用CHRT 0.35 μm salicide 2P4M工艺流片.     

一种6T像素全局曝光CMOS图像传感器

提出了一种基于6T像素结构的全局曝光CMOS图像传感器。通过采用PPD结构的6T像素、高复位电平和低阈值器件,提高了动态范围,并优化设计了像素单元的版图,使之获得较高的填充系数;模拟读出电路部分,通过采用双采样、增益放大和减小列级固定模式噪声(FPN)处理,以及对列选控制电路进行优化,减小了对全局PGA的运放设计要求。芯片的工作频率为20MHz,动态范围为66dB,实现了全局曝光方式CMOS图像传感器的设计。     

高帧频高灵敏度线列PIN-CMOS图像传感器研究

设计了一款高帧频高灵敏度双通道16元线列PIN-CMOS图像传感器。相对于传统的pn结光电二极管,PIN光电二极管具有结电容小和量子效率高的优点,可以降低CTIA像素电路的噪声,提高信噪比;同时采用一种新型的相关双采样电路结构,可以在边积分边读出的模式下实现相关双采样,抑制像素复位带来的KTC噪声。基于0.35μm PIN-CMOS工艺进行了线列CMOS图像传感器流片,并对器件的光电性能进行了测试。测试结果表明:在像元尺寸为90μm×90μm,700nm波长下,器件灵敏度达3000V/(lx·s),量子效率为96%;在40kHz高帧频、0.05lx光照条件下器件信噪比为7,适于弱信号下的高速探测。     

基于4T结构的高灵敏度CMOS图像传感器设计

基于0.35μm工艺,设计了应用于低光照环境下的低噪声、高灵敏度CMOS图像传感器。该图像传感器采用PPD 4T像素结构,像素阵列512×512,包含列级运放、水平移位寄存器、逻辑控制单元、单斜率模数转换器和偏置电路等模块。通过采用低噪声PPD 4T像素结构、低噪声列级放大器电路结构,以及对版图的优化设计等措施实现了低噪声、高灵敏度的CMOS图像传感器设计。     

CMOS图像传感器时序控制方法研究与实现

针对CMOS图像传感器滚筒式曝光模式,研究采用多种曝光时间,实现多线段拟合像素输出特性曲线,扩展传感器的动态范围,并改善其平滑性,提高图像清晰度;应用电源保护环、像素二次采样等方法消噪。电路选用charter 0.35μm工艺,经仿真验证满足设计要求。     

包含交流耦合CTIA与数字CDS的CMOS图像传感器设计

设计了一种带隔直电容的交流耦合CTIA像元电路与数字相关双采样（DCDS）结构的CMOS图像传感器系统。在传统的CTIA像元电路中增加隔直电容,通过控制光电二极管的偏压,达到减小光电二极管暗电流的目的;同时采用片外数字CDS结构,通过在片外实现复位信号与像元积分信号的量化结果在数字域的减法,可以减小图像传感器像元的复位噪声和固定图案噪声（FPN）。基于0.35 m标准CMOS工艺对此CMOS图像传感器进行流片,像元阵列为256256,像元尺寸为16 m16 m。测试结果表明交流耦合CTIA像元电路可以将光电二极管的偏压控制在零偏点附近,此时其暗电流最小;采用了数字CDS结构后,图像传感器像元的时域噪声及固定图案噪声均有不同程度降低。     

一种用于非制冷红外焦平面阵列的低噪声高均匀性读出电路

提出了一种高均匀性低噪声的读出电路,该电路通过抑制非制冷红外焦平面阵列固定模式噪声,从而可实现高质量的红外图像.该电路前端采用了行共享的增益可控NMOS管抑制像元固定模式噪声,同时采用了新型的相关双采样电路抑制列固定模式噪声.在仿真基础上,采用了AMS 0.35μm CMOS工艺完成了16×16像元芯片的制备.对芯片的大量测试结果表明提出的读出电路可以有效地降低非制冷红外焦平面阵列的固定模式噪声,同时具有高均匀性的特点,适用于高性能非制冷红外探测器.     

一种用于非制冷红外焦平面阵列的低噪声高均匀性读出电路（英文）

提出了一种高均匀性低噪声的读出电路,该电路通过抑制非制冷红外焦平面阵列固定模式噪声,从而可实现高质量的红外图像.该电路前端采用了行共享的增益可控NMOS管抑制像元固定模式噪声,同时采用了新型的相关双采样电路抑制列固定模式噪声.在仿真基础上,采用了AMS 0.35μm CMOS工艺完成了16×16像元芯片的制备.对芯片的大量测试结果表明提出的读出电路可以有效地降低非制冷红外焦平面阵列的固定模式噪声,同时具有高均匀性的特点,适用于高性能非制冷红外探测器.     

DESIGN AND IMPLEMETTATION OF CMOS IMAGE SENSOR

A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35 μm process along with its design and implementation is introduced in this paper. The pixel architecture of Active Pixel Sensor (APS) is used in the chip, which comprises a 256×256 pixel array together with column amplifiers, scan array circuits, series interface, control logic and Analog-Digital Converter (ADC). With the use of smart layout design, fill factor of pixel cell is 43%. Moreover, a new method of Dynamic Digital Double Sample (DDDS) which removes Fixed Pattern Noise (FPN) is used.The CMOS image sensor chip is implemented based on the 0.35 μm process of chartered by Multi-Project Wafer (MPW). This chip performs well as expected.     

DESIGN AND IMPLEMENTATION OF CMOS IMAGE SENSOR

I. Introduction Complementary Metal Oxide Semiconductor (CMOS) image sensor has been becoming in-creasingly significant in the field of solid image sensor. Compared with Charge-Coupled Device (CCD) image sensor, CMOS image sensor possesses many advantages, such as smaller size, more con-venient to be integrated with other devices, lower power consumption and cost, etc[1,2]. To date, CMOS image sensor is adopted in almost all mo-biles which can take pictures. In addition, CMOS image …     

Research on Column FPN and Black Level Calibration in Large Array CMOS Image Sensor

A technical investigation, research and im-plementation is presented to correct column fixed pattern noise and black level in large array Complementary metal oxide semiconductor (CMOS) image sensor. Through making a comparison among reported solution, and give large array CMOS image sensor design and considerations, according to our previous analysis on non-ideal factor and error source of piecewise Digital to analog converter (DAC) in multi-channels, an improving accurate piecewise DAC with adaptive switch technique is developed. The research theory has verified by a high dynamic range and low column Fixed pattern noise (FPN) CMOS image sensor prototype chip, which consisting of 8320×8320 pixel array was designed and fabricated in 55nm CMOS 1P4M standard process. The chip active area is 48mm×48mm with a pixel size of 5.7μm×5.7μm. The measured results achieved a high intrinsic dynamic range of 75dB, a low FPN and black level of 0.06％, a low photo response non-uniformity of 1.5％ respectively, and an excellent raw sample image taken by the prototype sensor.     

Linear Current-Mode Active Pixel Sensor

A current mode CMOS active pixel sensor (APS) providing linear light-to-current conversion with inherently low fixed pattern noise (FPN) is presented. The pixel features adjustable-gain current output using a pMOS readout transistor in the linear region of operation. This paper discusses the pixel's design and operation, and presents an analysis of the pixel's temporal noise and FPN. Results for zero and first-order pixel mismatch are presented. The pixel was implemented in a both a 3.3 V 0.35 and a 1.8V 0.18 CMOS process. The 0.35 process pixel had an uncorrected FPN of 1.4%/0.7% with/without column readout mismatch. The 0.18 process pixel had 0.4% FPN after delta-reset sampling (DRS). The pixel size in both processes was 10times10 mum², with fill factors of 26% and 66%, respectively.     

CMOS有源像素传感器特性分析与优化设计

设计了一个三管有源像素和其用开关电容放大器实现的双采样读出电路.该电路被嵌入一64×64像素阵列CMOS图像传感器,在Chartered公司0.35μm工艺线上成功流片.在8μm×8μm像素尺寸下实现了57%的填充因子.测得可见光响应灵敏度为0.8V/(lux·s),动态范围为50dB.理论分析和实验结果表明随着工艺尺寸缩小,像素尺寸减小会使光响应灵敏度降低.在深亚微米工艺条件下,较深的n阱/p衬底结光电二极管可以提供合理的填充因子和光响应灵敏度.     

A 9-V/Lux-s 5000-frames/s 512/spl times/512 CMOS sensor

A high-responsivity 9-V/Lux-s high-speed 5000-frames/s (at full 512/spl times/512 resolution) CMOS active pixel sensor (APS) is presented in this paper. The sensor was designed for a 0.35-/spl mu/m 2P3M CMOS sensor process and utilizes a five-transistor pixel to provide a true parallel shutter. Column-parallel analog-to-digital converter (ADC) architecture yields fast readout from pixels and digitization of the data simultaneously with acquiring a new frame. The chip has a two-row SRAM to store data from the ADC and read previous rows of data out of the chip. There are a total of 16 parallel ports operating up to 90 MHz delivering /spl sim/1.3 Gpixel/s or 13 Gb/s of data at the maximum rate. In conclusion, a comparison between two high-speed digital CMOS sensor architectures, which are a column-parallel APS and a digital pixel sensor (DPS), is conducted.     

320×240 Pixels CMOS Digital Image Sensor with Wide Dynamic Range

A 320×240 CMOS image sensor is demonstrated,which is implemented by a standard 0.6 μm 2P2M CMOS process.For reducing the chip area,each 2×2-pixel block shares a sample/hold circuit,analog-to-digital converter and 1-b memory.The 2×2 pixel pitch has an area of 40 μm×40 μm and the fill factor is about 16%.While operating at a low frame rate,the sensor dissipates a very low power by power-management circuit making pixel-level comparators in an idle state.A digital correlated double sampling,which eliminates fixed pattern noise,improves SNR of the sensor, and multiple sampling operations make the sensor have a wide dynamic range.     

A pixel size shrinkage of amplified MOS imager with two-line mixing

This paper describes a pixel size shrinkage of an amplified MOS image sensor (AMI). We have developed a new circuit technique to achieve the reduction of a pixel size while realizing vertical two-line mixing and high sensitivity. A 1/4-in format 250-k pixel image sensor was developed using a 0.8-μm CMOS process. The difference from the conventional CMOS process is an additional layer of ion-implantation process. The power supply voltages of this imager are 4 and 6 V. The dynamic range of 75 dB, the sensitivity of 1.8 μA/Ix, and the smear noise of less than -120 dB have been attained for the pixel size of 7.2 (H)×5.6 (V) μm². Although the measured fixed pattern noise ratio (FPN) of this imager is -55 dB, analysis with a test chip shows that FPN can be improved by 2 dB by adopting a suitable gate length for amplifier and resetting MOSFET, respectively