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1.
A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35 μm process along with its design and implementation is introduced in this paper. The pixel architecture of Active Pixel Sensor (APS) is used in the chip, which comprises a 256×256 pixel array together with column amplifiers, scan array circuits, series interface, control logic and Analog-Digital Converter (ADC). With the use of smart layout design, fill factor of pixel cell is 43%. Moreover, a new method of Dynamic Digital Double Sample (DDDS) which removes Fixed Pattern Noise (FPN) is used.The CMOS image sensor chip is implemented based on the 0.35 μm process of chartered by Multi-Project Wafer (MPW). This chip performs well as expected. 相似文献
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介绍了基于0.35μm工艺设计的单片CMOS图像传感器芯片.该芯片采用有源像素结构,像素单元填充因数可达到43%,高于通常APS结构像素单元30%的指标.此外还设计了一种数字动态双采样技术,相对于传统的双采样技术(固定模式噪声约为0.5%),数字动态双采样技术具有更简洁的电路结构和更好抑制FPN噪声的效果.传感器芯片通过MPW计划采用Chartered 0.35μm数模混合工艺实现.实验结果表明芯片工作良好,图像固定模式噪声约为0.17%. 相似文献
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A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters 总被引:4,自引:0,他引:4
Furuta M. Nishikawa Y. Inoue T. Kawahito S. 《Solid-State Circuits, IEEE Journal of》2007,42(4):766-774
This paper presents a high-speed, high-sensitivity 512times512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a charge amplifier for high charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integrated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-mum CMOS image sensor technology achieves the full frame rate in excess of 3500 frames/s. The in-pixel charge amplifier achieves the optical sensitivity of 19.9 V/lxmiddots. The signal full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8mVrms, and the resulting signal dynamic range is 60 dB 相似文献
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Liu Yu Wang Guoyu 《电子科学学刊(英文版)》2007,24(1):95-99
I. Introduction Complementary Metal Oxide Semiconductor (CMOS) image sensor has been becoming in-creasingly significant in the field of solid image sensor. Compared with Charge-Coupled Device (CCD) image sensor, CMOS image sensor possesses many advantages, such as smaller size, more con-venient to be integrated with other devices, lower power consumption and cost, etc[1,2]. To date, CMOS image sensor is adopted in almost all mo-biles which can take pictures. In addition, CMOS image … 相似文献
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We present a monolithic ultraviolet(UV) image sensor based on a standard CMOS process.A compact UV sensitive device structure is designed as a pixel for the image sensor.This UV image sensor consists of a CMOS pixel array,high-voltage switches,a readout circuit and a digital control circuit.A 16×16 image sensor prototype chip is implemented in a 0.18μm standard CMOS logic process.The pixel and image sensor were measured. Experimental results demonstrate that the image sensor has a high sensitivity of 0.072 V/(mJ/cm~2) and can capture a UV image.It is suitable for large-scale monolithic bio-medical and space applications. 相似文献
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A 320×240 CMOS image sensor is demonstrated,which is implemented by a standard 0.6 μm 2P2M CMOS process.For reducing the chip area,each 2×2-pixel block shares a sample/hold circuit,analog-to-digital converter and 1-b memory.The 2×2 pixel pitch has an area of 40 μm×40 μm and the fill factor is about 16%.While operating at a low frame rate,the sensor dissipates a very low power by power-management circuit making pixel-level comparators in an idle state.A digital correlated double sampling,which eliminates fixed pattern noise,improves SNR of the sensor, and multiple sampling operations make the sensor have a wide dynamic range. 相似文献
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CMOS图像传感器固定模式噪声抑制新技术。 总被引:1,自引:0,他引:1
针对有源像素(APS)CMOS图像传感器中的固定模式噪声(FPN),设计了一种动态数字双采样的噪声抑制新技术;该技术比普通双采样技术具有更佳的抑制效果,其电路结构简单,适合于像素尺寸不断缩小的CMOS图像传感器发展趋势。通过MPW计划,采用Chartered0.35μmCMOS工艺制作了测试ASIC芯片,试验结果表明动态数字双采样技术有效抑制了FPN噪声。 相似文献
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An improved global shutter pixel structure with extended output range and linearity of compensation is proposed for CMOS image sensor. The potential switching of the sample and hold capacitor bottom plate outside the array is used to solve the problem of the serious swing limitation, which will attenuate the dynamic range of the image sensor. The non-linear problem caused by the substrate bias effect in the output process of the pixel source follower is solved by using the mirror FD point negative feedback self-establishment technology outside the array. The approach proposed in this paper has been verified in a global shutter CMOS image sensor with a scale of 1024×1024 pixels. The test results show that the output range is expanded from 0.95V to 2V, and the error introduced by the nonlinearity is sharply reduced from 280mV to 0.3mV. Most importantly, the output range expansion circuit does not increase the additional pixel area and the power consumption. The power consumption of linearity correction circuit is only 23.1μW, accounting for less than 0.01% of the whole chip power consumption. 相似文献
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设计了一种带隔直电容的交流耦合CTIA像元电路与数字相关双采样(DCDS)结构的CMOS图像传感器系统。在传统的CTIA像元电路中增加隔直电容,通过控制光电二极管的偏压,达到减小光电二极管暗电流的目的;同时采用片外数字CDS结构,通过在片外实现复位信号与像元积分信号的量化结果在数字域的减法,可以减小图像传感器像元的复位噪声和固定图案噪声(FPN)。基于0.35 m标准CMOS工艺对此CMOS图像传感器进行流片,像元阵列为256256,像元尺寸为16 m16 m。测试结果表明交流耦合CTIA像元电路可以将光电二极管的偏压控制在零偏点附近,此时其暗电流最小;采用了数字CDS结构后,图像传感器像元的时域噪声及固定图案噪声均有不同程度降低。 相似文献
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设计了一种基于电容反馈跨阻放大器(CTIA)的长线列CMOS图像传感器。为减小器件功耗和面积,采用基于单端四管共源共栅运算放大器。为提高信号读出速率,采用没有体效应的PMOS源跟随器,同时减小PMOS管的宽长比,有效减小了输出总线寄生电容的影响。在版图设计上,采用顶层金属走线,降低寄生电阻和电容,提高了长线列CMOS图像传感器的读出速率和输出线性范围。采用0.35μm 3.3V标准CMOS工艺对传感器进行流片,得到器件像元阵列为5×1 030,像元尺寸为20μm×20μm。测试结果表明:该传感器在积分时间为1ms、读出速率为4MHz的情况下工作稳定,其线性度达到98%,线性动态范围为76dB。 相似文献
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Linear Current-Mode Active Pixel Sensor 总被引:1,自引:0,他引:1
《Solid-State Circuits, IEEE Journal of》2007,42(11):2482-2491
A current mode CMOS active pixel sensor (APS) providing linear light-to-current conversion with inherently low fixed pattern noise (FPN) is presented. The pixel features adjustable-gain current output using a pMOS readout transistor in the linear region of operation. This paper discusses the pixel's design and operation, and presents an analysis of the pixel's temporal noise and FPN. Results for zero and first-order pixel mismatch are presented. The pixel was implemented in a both a 3.3 V 0.35 and a 1.8V 0.18 CMOS process. The 0.35 process pixel had an uncorrected FPN of 1.4%/0.7% with/without column readout mismatch. The 0.18 process pixel had 0.4% FPN after delta-reset sampling (DRS). The pixel size in both processes was 10times10 mum2, with fill factors of 26% and 66%, respectively. 相似文献
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Yamawaki M. Kawashima H. Murata N. Andoh F. Sugawara M. Fujita Y. 《Electron Devices, IEEE Transactions on》1996,43(5):713-719
This paper describes a pixel size shrinkage of an amplified MOS image sensor (AMI). We have developed a new circuit technique to achieve the reduction of a pixel size while realizing vertical two-line mixing and high sensitivity. A 1/4-in format 250-k pixel image sensor was developed using a 0.8-μm CMOS process. The difference from the conventional CMOS process is an additional layer of ion-implantation process. The power supply voltages of this imager are 4 and 6 V. The dynamic range of 75 dB, the sensitivity of 1.8 μA/Ix, and the smear noise of less than -120 dB have been attained for the pixel size of 7.2 (H)×5.6 (V) μm2. Although the measured fixed pattern noise ratio (FPN) of this imager is -55 dB, analysis with a test chip shows that FPN can be improved by 2 dB by adopting a suitable gate length for amplifier and resetting MOSFET, respectively 相似文献
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设计了一种用于CMOS图像传感器的列并行RSD循环ADC.转换和采样同步进行,速度比传统的循环ADC提高了1倍,适用于高速实时系统的应用.将采样保持,精确乘2和像素信号的FPN噪声消除功能用1个运放和6个电容来实现,大大缩小了面积.采用RSD算法,不但降低了对比较器的精度要求,并且实现了较高的线性度.通过失调反向存储,基本消除运放失调引入的列FPN噪声.该ADC在0.18μm工艺下,实现了10位精度和500 KS/S的高转换速度.ADC的DNL= 0.5/-0.5 LsB,INL= 0.1/-1.5 LSB. 相似文献
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设计了一种基于电容反馈跨阻放大器型(Capacitive Trans-impedance Amplifier,CTIA)像元电路与双采样(Delta Double Sampling,DDS)的低照度CMOS图像传感器系统。采用CTIA像元电路提供稳定的光电二极管偏置电压以及高注入效率,完成在低照度情况下对微弱信号的读取;同时采用数字DDS结构,通过在片外实现像元积分信号与复位信号的量化结果在数字域的减法,达到抑制CMOS图像传感器中固定图案噪声的目的,进一步提高低照度CIS的成像质量。基于0.35 m标准CMOS工艺对此基于CTIA像元电路的CMOS图像传感器芯片进行流片,像元阵列为256256,像元尺寸为16 m16 m。测试结果表明该低照度CMOS图像传感器系统可探测到0.05 lx光照条件下的信号。 相似文献
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《IEEE transactions on circuits and systems. I, Regular papers》2008,55(9):2561-2572
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Matsuo S. Bales T.J. Shoda M. Osawa S. Kawamura K. Andersson A. Munirul Haque Honda H. Almond B. Yaowu Mo Gleason J. Chow T. Takayanagi I. 《Electron Devices, IEEE Transactions on》2009,56(11):2380-2389
An 8.9-megapixel 60-frames/s video image sensor with a 14-b column-parallel analog-to-digital converter (ADC) has been developed. A gain amplifier, a 14-b successive approximation ADC (SA-ADC), and a new column digital processor are employed in each column. The SA-ADC has sufficient operation speed to convert the pixel reset and the pixel signal into digital data in a row operation cycle. The column digital processor receives bit serial data from the SA-ADC output and performs subtraction of the reset data from the signal data in order to reduce column fixed pattern noise (FPN). Column FPN is successfully reduced to 0.36 erms - by this digital-domain column FPN correction. Low-voltage low-power serial video interface and noise decoupling on pixel drive voltages contribute to row-temporal-noise reduction to 0.31 erms -. Both column FPN and row temporal noise are not visible in spite of a low readout noise floor of 2.8 erms -. 相似文献
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Kavadias S. Dierickx B. Scheffer D. Alaerts A. Uwaerts D. Bogaerts J. 《Solid-State Circuits, IEEE Journal of》2000,35(8):1146-1152
CMOS image sensors with logarithmic response are attractive devices for applications where a high dynamic range is required. Their strong point is the high dynamic range. Their weak point is the sensitivity to pixel parameter variations introduced during fabrication. This gives rise to a considerable fixed pattern noise (FPN) that deteriorates the image quality unless pixel calibration is used. In the present work a technique to remove the FPN by employing on-chip calibration is introduced, where the effect of threshold voltage variations in pixels is cancelled. An image sensor based on an active pixel structure with five transistors has been designed, fabricated, and tested. The sensor consists of 525×525 pixels measuring 7.5 μm×10 μm, and is fabricated in a 0.5-μm CMOS process. The measured dynamic range is 120 dB while the FPN is 2.5% of the output signal range 相似文献
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Tanzer M. Graupner A. Schuffny R. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2004,51(10):566-570
Three different current-mode-output CMOS image sensor structures comprising of a pixel cell and an appropriate readout circuit have been analyzed and compared with regard to their noise behavior, fixed-pattern noise (FPN), and the dynamic range. First, a standard integrating pixel cell with a readout circuit containing a voltage-to-current converter is proposed. Second, a pixel cell based on a switched current cell is analyzed. The third sensor cell uses a feedback loop to control the reverse bias voltage of the photodiode to reduce the settling time of the pixel cell and the influence of the photodiodes's dark current. The necessary amplifier is partly located in the pixel cell and partly in the readout circuit. In all sensors, correlated double sampling is used to suppress the FPN. 相似文献