一种中速高精度模拟电压比较器的设计

设计一种中速高精度模拟电压比较器,该比较器采用3级前置放大器加锁存器和数字触发电路的多级结构,应用失调校准技术消除失调,应用共源共栅结构抑制回程噪声干扰;应用数字触发电路获得高性能数字输出信号,设计采用0.35μm 5 V CMOS工艺实现一个输入电压2.5 V、速度1 MS/s、精度12位的逐次逼近型A/D转换器.Hspice仿真结果表明:在5 V供电电压下,速度可达20 MHz,准确比较0.2 mV电压,有效校准20 mV输入失调,功耗约1 mW.     

一种0.2-mV 20-MHz 600-μW比较器

提出了一种低功耗中速高精度比较器。比较器采用3级前置放大器加锁存器的多级结构,应用失调校准技术,用于一个电压2.5 V、速度1 MS/s、精度12位的逐次逼近型A/D转换器。该比较器采用UMC 0.18μm混合模式3.3 V CMOS工艺设计制造。仿真结果表明,在2.5 V电压下,速度可以达到20 MHz,准确比较0.2 mV电压,并能有效校准20 mV输入失调,功耗仅为600μW,版图面积为620μm×190μm。     

面向存算ADC阵列的比较器失调校准电路

提出了一种面向存算模数转换器(ADC)阵列的动态比较器全局失调校准电路,采用数字辅助的模拟微调技术,并结合阵列式应用特点全局共用校准电压.校准过程分为粗校准和细校准周期,提高了校准速度和精度.粗校准利用6-bit计数器和数模转换器(DAC)产生阶梯式校准电压,根据初始失调电压极性将校准电压连接至对应的电流补偿电路,通过较大的校准步长快速减小失调电压值,并改变其极性.细校准采用一种基于晶体管栅压调控的延时可调电路,通过10-bit计数器和DAC产生细校准电压,实现失调电压值的精细调整.基于简单门电路和触发器设计比较器校准逻辑电路,在全局校准信号的控制下,实现本地校准开关和校准周期的转换.通过校准电压发生电路的全局共用,比较器只需要增加校准逻辑电路、电流补偿电路和延时可调电路,从而减小了由校准电路导致的面积开销.基于55 nm互补金属氧化物半导体(CMOS)工艺的仿真结果表明,在输入时钟50 MHz条件下,失调校准范围±20 mV,校准后失调电压0.96 mV(3.3σ),阵列校准后失调电压呈现出较为均匀的分布,包含校准电路的比较器版图面积为696.28μm².     

具有带隙结构的迟滞比较器电路设计

基于LED驱动的微功耗DC—DC转换器,针对低压高稳定性的要求设计了一款具有带隙结构的迟滞比较器电路,它的最低输入电压为1．2V,其核心电路有带隙基准比较器、射极跟随器和迟滞比较器。整个电路采用Bipolar工艺设计,利用HSpice软件对所设计的电路进行了仿真与验证。结果表明,迟滞比较器的迟滞电压为8mV,翻转门限电压随输入电压和温度的变化均很小。     

一种比较器电路的自动失调补偿方法

文章提出了一种适用于高精度传感器和高精度模数转换器的比较器电路。该电路利用失调自动补偿技术提高了比较器的精度,该补偿技术不需要增加前置放大器的增益,也不需要增加静态电流,从而获得低噪声和低功耗。电路设计和Hspice仿真基于CSMC0．5μm CMOS工艺,电源电压3．3V。仿真结果表明,在时钟为100kHz、电源电压为3．3V下补偿之后的比较器的失调较补偿前由原来的9．75mV降低为0．31mV。     

低功耗高精度的电压比较器设计

设计了一款用于实现10位精度逐次逼近型模数转换器(SAR ADC)的电压比较器,该比较器采用高速高精度比较器结构并进行了优化,在高速度、低功耗锁存器的基础上加预放大级以提高比较精度,加RS触发器优化处理比较器的输出信号。同时,采用失调校准技术消除失调,预放大级采用共源共栅结构抑制回程噪声,最终获得了高精度和较低的功耗。仿真结果表明:在Chartered 0.35μm 2P4MCMOS工艺下,时钟频率5 MHz,电源电压3.3 V,分辨率达0.1 mV,平均功耗约为0.45 mW,芯片测试结果表明比较器满足了SAR ADC的要求。     

用于16位流水线ADC的高速动态比较器设计

介绍一种用于16位100MS/s流水线ADC中第一级子ADC的开关电容高速动态比较器电路,在传统的前置放大器加锁存比较电路结构的基础上,设计再生比较器的复位信号,增加失调消除反馈环路,当输入信号在各基准电压判定点附近一定范围内时交叉输出0、1电平,一方面均衡噪声,另一方面消除因工艺制造失配等带来的失调误差的影响。电路采用0.18μm 1.8V1P5MCMOS工艺,在1.8V条件下传输延时约300ps,转换速率约100ps,功耗约250μA,失调电压仅约0.2mV,可以满足16位流水线ADC对比较器性能的要求。     

低踢回噪声锁存比较器的分析与设计

设计了一种低踢回噪声锁存比较器，着重分析和优化了比较器的速度和失调电压。在0.35μm CMOS工艺条件下，采用Hspice对电路进行了模拟。结果表明，比较器的最高工作频率为200MHz，分辨率在6位以上，灵敏度为0．3mV；在2．5V电源电压下，功耗为70μW。     

基于0.18 μm CMOS工艺的超高速比较器

给出了基于TSMC 0．18μm CMOS工艺的1．8V超高速比较器的设计方案；对比较器速度和失调进行综合，设计了一个1GHz超高速低失调比较器；通过Monte Carlo仿真，验证该比较器的失调电压分布范围为-4．5～4．5mV，并进行了版图设计。该比较器应用于低电压A／D转换器设计中，可达到6位以上的精度。     

宽输入共模范围电压比较器的设计

当输入信号的共模值超过或者接近电源电压时,传统的电压比较器就会出现不足,因此有必要设计新的比较器来实现对高共模信号的检测.采用了共栅差分输入级,极大地增加了输入共模信号的范围.基于此输入级设计了两个电压比较器,一个在锂电池充电电路中实现了对电池和电源电压的监控,另一个响应速度快.CSMC 0.6 μm CMOS工艺的仿真结果表明,前者能简便的实现输入失调和迟滞控制功能,静态电流仅为1.2 μA;后者在单电源5 V下输入共模范围是1.3～15 V,在10 mV的过驱动电压下,延时为11 ns,静态工作电流为91 μA.     

1.5 μm CMOS gate arrays with analog/digital macros designedusing common base arrays

Mixed analog and digital circuits are realized on a 1.5 μm silicon-gate CMOS chip with +5 V power supply only. The circuit uses CMOS digital gate arrays of 0.32 K to 19.6 K cells and is created without any additional turnaround time or any restriction on the design. Typical internal digital gate (two-input NAND) speed, with a fanout of 3 and a wire length of 3 mm, is 1.4 ns. A voltage comparator with ±8 mV maximum input offset voltage and 60 ns response time, digital-to-analog and analog-to-digital converters with 4-, 6-, and 8-bit resolution, respectively, and an analog switch of 25 Ω on-resistance can be realized on the same chip with digital circuits. Using this technology, about one-tenth of the turnaround time can be achieved compared with full-custom LSIs for the same system. The product development flow and computer-aided-design tools for designing mixed analog and digital gate arrays are the same as for digital gate arrays     

A 0.5 V offset cancelled latch comparator in standard 0.18 μm CMOS process

This paper presents a new 0.5 V high-speed dynamic latch comparator with built-in foreground offset cancellation capability and rail-to-rail input range. Traditional latch comparators lose their speed performance in low voltage condition, especially in sub-1V applications. The proposed latch comparator utilizes a speed-up technique based on a novel boosting method to mitigate the low voltage imperfections on circuit operation. Employing a new offset cancellation technique based on the same boosting capacitors is another key idea. This enhances the accuracy of the ultra low-voltage latch comparators and relaxes the need for preamplifier stage, which is conventionally used in the low offset latch comparator. The performed Monte Carlo simulations over corners in 0.18 μm standard CMOS process show the improvement of input referred offset voltage with a standard deviation of 29.9 mV/299 μV before and after offset cancellation, respectively. The designed comparator dissipates 34 μW power from 0.5 V voltage supply while operating in 200 MHz clock frequency and detects 1 mV input difference.     

A novel low-power,low-offset,and high-speed CMOS dynamic latched comparator

A novel dynamic latched comparator with offset voltage compensation is presented. The proposed comparator uses one phase clock signal for its operation and can drive a larger capacitive load with complementary version of the regenerative output latch stage. As it provides a larger voltage gain up to 22 V/V to the regenerative latch, the input-referred offset voltage of the latch is reduced and metastability is improved. The proposed comparator is designed using 90 nm PTM technology and 1 V power supply voltage. It demonstrates up to 24.6% less offset voltage and 30.0% less sensitivity of delay to decreasing input voltage difference (17 ps/decade) than the conventional double-tail latched comparator at approximately the same area and power consumption. In addition, with a digitally controlled capacitive offset calibration technique, the offset voltage of the proposed comparator is further reduced from 6.03 to 1.10 mV at 1-sigma at the operating clock frequency of 3 GHz, and it consumes 54 μW/GHz after calibration.     

A Wireless Power Interface for Rechargeable Battery Operated Medical Implants

This brief presents a highly integrated wirelessly powered battery charging circuit for miniature lithium (Li)-ion rechargeable batteries used in medical implant applications. An inductive link and integrated Schottky barrier rectifying diodes are used to extract the DC signal from a power carrier while providing low forward voltage drop for improved efficiency. The battery charger employs a new control loop that relaxes comparator resolution requirements, provides simultaneous operation of constant-current and constant-voltage loops, and eliminates the external current sense resistor from the charging path. The accuracy of the end-of-charge (EOC) detection is primarily determined by the voltage drop across matched resistors and current-sources and the offset voltage of the sense comparator. Experimental results in 0.6-mum 3M-2P CMOS technology indicate that plusmn1.3% (or plusmn20 muA) EOC accuracy can be obtained under worst case conditions for a comparator offset voltage of plusmn5 mV. The circuit measures roughly 1.74 mm² and dissipates 8.4 mW in the charging phase while delivering a load current of 1.5 mA at 4.1 V (or 6.15 mW) for an efficiency of 73%.     

An offset cancellation technique for comparators using body-voltage trimming

A novel offset cancellation technique based on body-voltage trimming is presented to be used in the comparators employed in high-speed analog-to-digital converters (ADCs) such as Flash ADCs. The proposed offset cancellation is achieved by body-voltage adjustment using a low-power simple analog control feedback circuit without any additional capacitive loading at the comparator output or complicated digital calibration scheme. The accuracy of the proposed technique is higher than its digital calibration counterparts due to its analog nature. Simulation results in a 1.8?V 0.18???m CMOS technology show that using the proposed technique the standard deviation of the comparator offset is significantly reduced from 36.2 to 7.1?mV operating at 1?GHz with only 32???W of power dissipation in the offset cancellation circuit.     

A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V

A comparator in a low-power 65-nm complementary metal–oxide–semiconductor process (only standard transistors with threshold voltage $V_{t} approx 0.4 hbox{V}$ were used) is presented, where the circuit of a conventional latch-type comparator consisting of two cross-coupled inverters is modified for fast operation, even with 0.6 GHz at a low supply voltage of 0.65 V. The advantages of a high-impedance input, rail-to-rail output swing, robustness against the influence of mismatch, and no static power consumption are kept. To achieve a bit error rate of $10^{-9}$ at 1.2-V supply, an amplitude at the input of 16.5 mV at 4 GHz has to be applied. If the supply voltage is lowered, 12.1 mV at 0.6 GHz/0.65 V is necessary. The power consumption of the comparator is 2.88 mW at 5 GHz (1.2 V) and 128 $muhbox{W}$ at 0.6 GHz (0.65 V). Simulations show an offset standard deviation of about 6.1 mV at 0.65-V supply. With an on-chip measurement circuit, the delay time of the comparator of, e.g., 104 ps for 15-mV input amplitude at 1.2-V supply, is obtained.      

An Offset Compensated Sampled-Data CMOS Comparator Circuit for Low-Power Implantable Biosensor Applications

This paper proposes a new low-voltage high resolution complementary metal oxide semiconductor (CMOS) comparator circuit suitable for biosensor applications. The comparator compensates for differential input offset through single-ended sampled-data preamplification. Simulations were carried out using a 130 nm IBM CMOS (CMRF8SF) process technology. Monte Carlo simulations incorporating mismatch between devices (based on width and length of devices) indicate that the design is quite robust. The comparator has a differential input overdrive resolution of under 1 mV and a response time which is scalable. The capacity for offset compensation trades with the bandwidth of the comparator through the size of the device channel areas (Width × Length) of the transistors. The static micropower consumed by the comparator from a 0.5 V supply voltage is under 10 μW, making it extremely suitable for miniaturized implantable biosensor devices. In addition, the comparator uses a single clock scheme for the sampled-data operations, which eliminates the need for special clock generation circuitry.     

基于数字电位器的可编程电压基准源设计

在电子设计中为了灵活准确地设置电压基准值,设计了可编程电压基准源电路。详细阐述了电路的设计思路和工作原理。利用5片2.048 V带隙电压基准源芯片串联产生10.24 V电压作为基准。随后创新地利用单片机控制1024抽头的数字电位器对基准电压进行分压,结合精准运放的反向放大电路,最后输出-10.24 V到10.22 V的可编程精准电压值,输出电压分辨力达20 mV。测试结果表明,该电路具有输出线性度好、精度高、性能稳定等优点。     

Threshold difference compensated sense amplifier

A dynamic flip-flop sense amplifier compensating for threshold difference between a pair of transistors by way of offset storage technique is presented. The DC and AC analyses on input offset voltage and performance limitations are discussed. Experimental results have shown that input offset is less than 2 mV with a 5 V single power supply, over a wide temperature range and a wide common mode input voltage range.