A new current-differencing single-supply operational amplifier

The conventional integrated-circuit operational amplifier is not well suited to many system applications that operate from only a single power supply voltage. To more optimally meet the requirements of industrial control systems a new current- differencing opamp has been developed that uses a simple circuit to provide a gain element that out performs the 741 IC opamp. As a result of the circuit simplicity, multiple opamps are possible and six independent internally compensated amplifiers have been fabricated on a single 80/spl times/93-mil die. Many circuits are presented only not to show how this circuit can perform most the application functions of a standard IC opamp, but also to indicate the increased usefulness of this new input current differencing type of opamp circuit in single power-supply control system applications.     

Modified Wien-bridge oscillator for chaos

A nonlinear Wien-bridge based circuit generating chaotic oscillations is reported. The generator contains a single opamp and a single nonlinear device displaying a current saturation characteristic. The oscillator is described by a set of three ordinary differential equations. Experimental results are included demonstrating the circuit performance     

An Over-60 dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp With Only 30 dB Loop Gain

Correlated level shifting (CLS) is introduced as a new switched-capacitor technique to provide true rail-to-rail performance while reducing errors from finite opamp gain. There is negligible kT/C noise increase and in many cases a speed advantage compared to using a high gain opamp. The gain enhancement is quantified with formulas and the general technique is compared to correlated double sampling (CDS). Results are presented from a 0.18 $~mu{hbox {m}}$ CMOS testchip of a 20 MHz, 12-bit pipelined A/D converter using CLS to reduce errors from finite opamp dc gain and limited opamp swing. It achieves 10.5 ENOB operating beyond the supply rails using an opamp circuit with 30 dB loop gain and 0.9 V supply.      

Reversed nested Miller compensation with voltage buffer and ing resistor

This paper presents a new reversed nested Miller compensation technique for multistage operational amplifier (opamp) design. The new compensation technique inverts the sign of the right half complex plane zero and shifts the frequency of the complex conjugate poles to a higher frequency. Simulation results indicate that the gain-bandwidth product and settling time are improved by factors of two and three, respectively, without degrading stability and power consumption. To verify the proposed technique, a three-stage opamp is fabricated with 0.6-/spl mu/m CMOS technology. The measured results of the test circuit agree with the results that are obtained from theoretical analysis and circuit simulation.     

一种低噪声高共模抑制比运算放大器的分析与设计

低噪声高共模抑制比的运算放大器是将套筒式共源共栅结构、差分输出和共模负反馈相结合,设计出的一种新型运算放大器.基于SMIC0.18 μm工艺模型对电路进行设计,仿真结果表明该电路的开环增益为82.3 dB,相位裕度为66°,共模抑制比为122 dB,增益平坦带宽为15 MHz,噪声为7.781 nV/sqrt （Hz）,达到设计要求.     

Prediction of high-power EMI effects in CMOS operational amplifiers

In this paper, a new analytical model for the prediction of the effects of high-power electromagnetic interference in CMOS operational amplifiers is presented. This model provides a closed-form expression of the operational amplifiers (opamp) output offset voltage that is induced if radio frequency interference (RFI) is superimposed onto the opamp input voltages in terms of technology and design parameters. Such a model is very useful both to predict the susceptibility of a given opamp circuit and to design opamp topologies with a high immunity to RFI. Model predictions are compared with experimental results.     

Configurable CMOS multiplier/divider circuits for analog VLSI

The design of five simple CMOS opamp based multipler/divider circuits is presented. Each two opamp and six MOSFET transistor circuit simultaneously achieves four-quadrant multiplication and division. Applications of the new circuits in analog signal processing and neural networks are discussed. The multiplier/divider circuits are all insensitive to MOS intrinsic parasitic capacitances. They do, however, exhibit different sensitivities to opamp finite unity-gain bandwidth. These sensitivities may be mitigated using the configurability property of the circuits. Finally experimental results are provided to support some of the theoretical claims.     

Design Procedure for Two-Stage CMOS Opamp With Flexible Noise-Power Balancing Scheme

This paper presents a basic two-stage CMOS opamp design procedure that provides the circuit designer with a means to strike a balance between two important characteristics in electronic circuit design, namely noise performance and power consumption. It is shown in this paper that, unlike the previously reported design procedures, the proposed design step allows opamp designers to trade between noise performance and power consumption with greater flexibility. In order to verify the viability of the proposed design step, SPICE simulation results of the opamp designed by the proposed procedure, under a variety of temperature and process conditions, are given.     

Direct-Charge-Transfer Pseudo-N-Path SC Circuit Insensitive to the Element Mismatch and Opamp Nonidealities

A novel pseudo-N-path switched-capacitor circuit is described. Its center frequency is insensitive to element mismatch as well as to the finite gain and bandwidth of the opamps used. In this new architecture, the charges from the input source to the output are not transferred by an opamp; rather the opamp is used only as a buffer. The performance of the circuit is superior to that of a regular pseudo-N-path structure.     

1-V 9-bit pipelined switched-opamp ADC

A 9-bit 1.0-V pipelined analog-to-digital converter has been designed using the switched-opamp technique. The developed low-voltage circuit blocks are a multiplying analog-to-digital converter (MADC), an improved common-mode feedback circuit for a switched opamp, and a fully differential comparator. The input signal for the converter is brought in using a novel passive interface circuit. The prototype chip, implemented in a 0.5-μm CMOS technology, has differential nonlinearity and integral nonlinearity of 0.6 and 0.9 LSB, respectively, and achieves 50.0-dB SNDR at 5-MHz clock rate. As the supply voltage is raised to 1.5 V, the clock frequency can be increased to 14 MHz. The power consumption from a 1.0-V supply is 1.6 mW     

An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs

A decoupling circuit using an operational amplifier is proposed to suppress substrate crosstalk in mixed-signal system-on-chip (SoC) devices. It overcomes the parasitic inductance problem of on-chip capacitor decoupling. The effect of the proposed decoupling circuit is not limited by parasitic fine impedance. A 0.13-/spl mu/m CMOS test chip showed that substrate noise at frequencies from 40 MHz to 1 GHz was incrementally suppressed by sequentially activating three of the proposed circuits in parallel. The power dissipation of each circuit was 3.3 mW at a 1.0-V power supply. The test chip measurement showed that the proposed decoupling reduced crosstalk by 31% at 200 MHz, whereas it was reduced by 4.4% with capacitor decoupling. This 7:1 ratio, or 17 dB, corresponds to the gain of the opamp. Design of the opamp and its feedback loop for active decoupling is simple, making the opamp useful for SoC applications.     

一个对温度不敏感的高增益运算放大器设计

功率放大器是大功率器件,其自身会消耗大部分的功耗,并导致功率放大器芯片的温度在一个很大的范围内变化,因此功率放大器的控制电路需要对环境温度的变化不敏感。针对这一要求,设计出一个对温度不敏感的全差分CMOS运算放大器,该运算放大器采用TSMC 0.18μm工艺,选用折叠式共源共栅、宽摆幅偏置电路结构。在负载电容为10 pF条件下,最大直流增益达到115 dBm,相位裕度为70°;在整个温度范围内（-40~＋125℃）运算放大器的增益变化仅为1 dBm,相位裕度仅变化5°,满足设计要求。     

Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters

The design of an ultra-low-voltage multistage (two-stage algorithmic) analog-to-digital converter (ADC) employing the opamp-reset switching technique is described. A highly linear input sampling circuit accommodates truly low-voltage sampling from external input signal source. A radix-based digital calibration technique is used to compensate for component mismatches and reduced opamp gain under low supply voltage. The radix-based scheme is based on a half-reference multiplying digital-to-analog converter structure, where the error sources seen by both the reference and input signal paths are made identical for a given stage. The prototype ADC was fabricated in a 0.18-/spl mu/m CMOS process. The prototype integrated circuit dissipates 9 mW at 0.9-V supply with an input signal range of 0.9 V/sub p-p/ differential. The calibration of the ADC improves the signal-to-noise-plus-distortion ratio from 40 to 55 dB and the spurious-free dynamic range from 47 to 75 dB.     

Current-mode divide-by-two circuit

A current-mode divide-by-two circuit is presented which does not rely on well matched components and a high gain opamp. The circuit can be employee as a reference-generating circuit of an algorithmic current-mode A/D convertor.<>     

嵌套式斩波运放的分析与设计

针对传统的斩波运放具有大残余失调的特点,设计了一个嵌套式斩波运放。基于SMIC0.18μm工艺,通过Spectre仿真工具进行验证与仿真,运放的开环增益达到78.3dB,共模抑制比达到112dB。在斩波频率fchophigh=10kHz、fchoplow=500Hz的条件下,通过使用非匹配斩波开关,分别对单斩波和嵌套式斩波运放进行仿真。结果表明,嵌套式斩波技术能有效减小残余失调的影响。适用于带宽较低的微弱信号检测与处理电路,如传感器前端读出电路和音频信号放大电路等。     

Optimisation of direct auto-zeroing offset cancellation in low voltage applications using dual level CMFB

A modified CMFB circuit is presented that reinstates the use of direct opamp auto-zeroing offset cancellation techniques in low voltage applications. This approach is particularly useful for high precision sample and hold amplifiers and Nyquist rate ADCs, where the opamp is reset during one of the clock phases. Differential offsets up to 50 mV are effectively reduced as demonstrated by a sample and hold example.     

一种带增益提高技术的高增益CMOS运算放大器的设计

给出了一种用在高速高精度流水线型模数转换器中的具有高增益和高单位增益频率的全差动CMOS运算放大器的设计,电路结构主要采用折叠式共源共栅结构,并采用增益提高技术提高放大器的增益。共模反馈电路由开关电容共模反馈电路实现。模拟结果显示,其开环直流增益可达到106 dB,在负载电容为2 pF时单位增益频率达到了167 MHz,满足了对模数转换器的高速度和高精度的要求。     

全差分增益提高运算放大器的分析与设计

通过增益提高技术,一个全差分增益提高套筒式共源共栅运算放大器被提出和设计。该运算放大器得主运算放大器是由全差分套筒式共源共栅放大器构成,并带有一个开关电容共模反馈电路。而增益提高放大器是由全差分析叠式共源共栅放大器构成,它的共模反馈电路是连续时间反馈电路。该运算放大器采用中芯国际0．35μmixed-signal CMOS工艺设计,运算放大器的直流增益可达到129dB,而单位增益频率为161MHz。     

A 1-V 1.8-MHz CMOS switched-opamp SC filter with rail-to-railoutput swing

A low-voltage switched capacitor (SC) filter operated from a single 1 V supply and realized in a standard 0.5-μm CMOS technology is presented. Proper operation is obtained using the switched-opamp technique without any clock voltage multiplier or low-threshold devices. This makes the circuit compatible with future deep submicrometer technology. As opposed to previous switched-opamp implementations, the filter uses a fully differential topology. This allows operation with a rail-rail output swing and reduction of the number of opamps required to build high order infinite impulse response (IIR) filters. On the other hand, a low-voltage common-mode feedback (CMFB) circuit is required. In addition, the circuit uses an opamp which is only partially turned off during the off phase. This enables an increase in the maximum sampling frequency. The filter implements a bandpass response (f_s/f _o=4, Q=7) and it has been characterized with a 1.8 MHz sampling frequency. Its power consumption is about 160 μW. The filter is still fully functional down to 0.9 V supply voltage     

Simple sinusoidal oscillator using opamp compensation poles

The Letter introduces a new, extremely simple, sinusoidal oscillator based on opamp compensation poles. The circuit employs only four components, two internally compensated opamps, one resistor and a grounded capacitor, and can generate sinusoidal oscillations of frequencies up to the gain bandwidth product of the opamps. with modification(s), using an additional opamp or two analogue multipliers, the circuit can be readily converted into a VCO. Experimental results and SPICE simulations have confirmed the workability of the various modes of operation of the proposed configuration.<>