0.15μm薄膜全耗尽MOS／SOI器件的设计和研制

利用自己开发的二维数值深亚微米SOI器件模拟软件,较为详细地分析了沟道长度小于o.2μm的 SOI器件的阈值电压特性、穿通和击穿特性、亚阈值特性以及直流稳态特性等.通过这些模拟和分析计算,给出了沟道长度为0.18、0.15和0.1μm的薄膜全耗尽 SOI／MOS器件的设计方案,并根据该设计方案成功地研制出了性能良好的沟道长度为0.15μm的凹陷沟道 SOI器件.沟道长度为0.15μm薄膜全耗尽凹陷沟道SOI器件的亚阈值斜率为87mV/dec,击穿电压为1.6V,阈值电压为0.42V,电源电压为1.5V时的驱动电流为1.85mA,泄漏电流为0.5pA/μm沟道宽度.     

薄膜厚度对钛酸钡类薄膜传感器敏感特性的影响

利用氩离子束溅射技术,分别在SiO2/Si衬底上淀积了0.5 mm、1 mm和2 mm的Ba1-xLaxNbyTi1–yO3薄膜,并探讨了薄膜厚度对MIS电容湿敏特性的影响以及薄膜厚度对薄膜电阻的光敏和热敏特性的影响。实验结果表明:0.5 mm膜厚的MIS电容传感器具有比2 mm膜厚的MIS电容传感器高9倍的湿敏灵敏度。用孔隙率和孔径分布物理模型分析得出,薄膜越薄,膜的孔隙率越高,器件的湿敏灵敏度越高。反之,薄膜越厚,光吸收越强,薄膜电阻的光敏灵敏度越高;但薄膜厚度对薄膜电阻热敏特性的影响甚微,敏感机理与薄膜的微观结构可解释这些现象。     

用SiO2气凝胶做隔热层的铁电薄膜红外探测器性能与铁电薄膜层厚度的关系

研究了铁电薄膜红外探测器响应率等器件参数随铁电薄膜厚度的变化.器件的隔热层结构采用气凝胶二氧化硅.实验发现器件的热释电系数,吸收率以及热导均随膜厚增加而增加.铁电膜层厚度为240nm的器件,其热导与微桥结构器件的热导相近,都为10-7W/K量级,证明气凝胶二氧化硅做隔热层能够制备出性能优良的热释电红外探测器.随着薄膜厚度增加,热导急剧增大,这是引起器件响应率降低的原因.制备铁电薄膜过程中的多次650°高温退火可能降低了二氧化硅多孔率.     

SOI工艺下不同薄膜厚度导致静电保护器件SCR维持电压漂移

由于SOI器件的特殊性质,在SOI工艺下对芯片进行静电保护设计是一件非常具有挑战性的工作。本文发现了当SCR在SOI工艺下作为静电保护器件时其薄膜厚度的变化会导致维持电压的漂移。文章通过0.18微米工艺下的流片实验验证了此现象并通过ISE TCAD器件仿真进行了模拟,对其机理进行了讨论。     

不同厚度PZT薄膜的制备及电性能特性研究

采用sol-gel（溶胶-凝胶）法在Pt/Ti/SiO2/Si基底上分别制备了厚度为400nm,600nm,800nm的PZT（锆钛酸铅,Zr/Ti=52/48）薄膜,研究了厚度对薄膜介电性能与铁电性能的影响。通过对薄膜的铁电性能与介电性能进行测试,分析了不同厚度薄膜的剩余极化强度、介电常数与介电损耗;通过对介电调谐率与最大正切损耗的计算,进一步分析了薄膜的介电调谐性能。实验结果表明,薄膜的介电常数与介电损耗随薄膜厚度的增大而增加;厚度为600nm的薄膜具有最好的介电调谐性能与铁电性能。     

薄膜厚度的EDS测量

薄膜厚度的ＥＤＳ测量赵家政徐洮（中国科学院兰州化学物理研究所固体润滑开放实验室，兰州７３００００）在电镀膜、真空蒸发膜、表面处理膜、溅射膜、润滑转移膜等的扫描电子显微分析中，除观察其表面形貌外，还希望同时测得薄膜的厚度。薄膜厚度的测量，尽管有光学法［...     

InGaAsP/InP外延薄膜折射率与厚度测量

本文报道一种应用波导耦合光栅测量InGaAsP/InP外延薄膜折射率与厚度的方法。该法测量精度高,具有非破坏性与工艺实时性优点。外延薄膜折射率与厚度测量精度分别可达到±2×10~(-3)与±1×10~(-2)μm,这完全满足DFB与DBR等一类半导体激光器以及有源导波光学器件的设计需要。     

薄膜厚度的电子探针测定

由于电子束的穿透本领很低,在使用较低的加速电压时更是如此,因此用电子探针测定薄膜厚度是很灵敏的。据估计,对重金属膜可测出nm量级的差别。关于电子探针测量有衬底薄膜厚度已有不少的文献报导,在此基础上,本文采用改变加速电压的方法,测量了不同衬底上,不同厚度铝薄膜的X射线归一化强度,画出归一化强度和加速电压的关系曲线,得出归一化强度恰等于1的电压值E_d,然后选择X射线激发深度公式,计算出薄膜的质量厚度。并将此结果与化学分析法,重量法等的试验结果,以及Monte Carlo模拟计算值加以比较,结果说明:电子探针测定有衬薄膜厚度是一种简易可行,又有着一定准确度的方法。     

漂移区为线性掺杂的高压薄膜SOI器件的研制

给出了漂移区为线性掺杂的高压薄膜SOI器件的设计原理和方法.在Si膜厚度为0.15μm、隐埋氧化层厚度为2μm的SOI硅片上进行了LDMOS晶体管的制作.首次对薄膜SOI功率器件的击穿电压与线性掺杂漂移区的杂质浓度梯度的关系进行了实验研究.通过对漂移区掺杂剂量的优化,所制成的漂移区长度为50μm的LDMOS晶体管呈现了高达612V的击穿电压.     

氮化铝薄膜的厚度对场发射特性的影响

采用射频磁控溅射方法,在n型(100)Si基底上沉积了不同厚度(20~150 nm)纤锌矿结构的纳米AlN薄膜。在超高真空系统中测量了不同膜厚样品的场发射特性,发现阈值电场随着厚度的增加有增大的趋势。厚度为44 nm的AlN薄膜样品具有最低的阈值电场(10 V/μm),当外加电场为35 V/μm时,最高发射电流密度为284μA/cm2。AlN薄膜场发射F-N曲线表明,在外加电场作用下,电子隧穿了AlN薄膜表面势垒发射到真空。     

硅膜厚度对0.1μm SOI槽栅NMOS器件特性的影响

SOI技术和槽栅MOS新器件结构是在改善器件特性方面的两大突破,SOI槽栅MOS器件结构能够弥补体硅槽栅MOS器件在驱动能力和亚阈值特性方面的不足,同时也保证了在深亚微米领域的抑制短沟道效应和抗热载流子效应的能力.仿真结果显示硅膜厚度对SOI槽栅MOS器件的阈值电压、亚阈值特性和饱和驱动能力都有较大影响,选择最佳的硅膜厚度是获得较好的器件特性的重要因素.     

Special mechanisms in thin-film SOI MOSFETs

The main special mechanisms that govern the operation of thin-film SOI MOSFETs are reviewed. The influence of the most important technological and electrical parameters, e.g. the film and buried oxide thicknesses, film and silicon substrate doping, channel length, substrate bias, and interface defects, is discussed. The electrical properties of fully depleted thin-film SOI MOS transistors are improved, especially the driving current and the subthreshold swing. We address the advantages of thin-film SOI devices in relation to scaling rules down to deep submicron transistors, as well as the main parasitic phenomena, e.g. the kink, latch, breakdown, self-heating and hot-carrier degradation effects. Finally, the low temperature properties and potential quantum effects are outlined.     

Semiconductor thickness and back-gate voltage effects on the gate tunnel current in the MOS/SOI system with an ultrathin oxide

The effects of the semiconductor layer thickness and the back-gate voltage on the current-voltage (I-V) characteristics of the MOS/SOI tunnel diode with an aluminum gate and n-type semiconductor layers are theoretically investigated. If the semiconductor thickness is reduced or the back-gate voltage is more negative, the total thermal generation current decreases and the gate-oxide thickness critical for transition from the quasiequilibrium strong inversion state to the nonequilibrium state increases. If the MOS/SOI tunnel diode is in the transition range between the nonequilibrium and quasiequilibrium states, a positive increase of the back-gate voltage V/sub BG/ results in a strong increase of the majority carrier tunnel current. This back-gate effect may be exploited in more functional devices based on the MOS/SOI tunnel diode.     

Analytical models of subthreshold swing and threshold voltage forthin- and ultra-thin-film SOI MOSFETs

Analytical models are proposed for thin- and ultra-thin film silicon-on-insulator (SOI) MOSFETs operating in weak or strong inversion. The models take into account all the device parameters. The cases of two and three interfaces with a silicon substrate are considered in the modeling and compared with one another. These models give the main electrical MOSFET parameters in ohmic operation (subthreshold swing and threshold voltage) for these structures. The basic approximation is the consideration of a linearly varying potential in the Si film, which has been inferred on the basis of numerical simulations. Various behaviors depending on the Si film and the buried insulator thickness as well as the interface charges, Si film doping, or substrate regime are simulated to assess the properties and the performances of SOI MOS transistors and to validate the analytical models     

SOI MOSFETI－V特性的计算机模拟

本文研究了ＳＯＩＭＯＳＦＥＴ的Ｉ－Ｖ特性，建立了一套模拟ＳＯＩ器件工作特性的解析模型，适用于不同的ＳＯＩ膜厚和各种前、背栅的偏置情况，在各种不同情况下由计算机自动选择适当模型进行拟合，该模型物理意义明确，计算简便快速，所用参数易于提取。     

薄膜SOI MOS器件阈值电压的解析模型分析

研究了薄膜全耗尽增强型 SOIMOS器件阈值电压的解析模型 ,并采用计算机模拟 ,得出了硅膜掺杂浓度和厚度、正栅和背栅二氧化硅层厚度及温度对阈值电压影响的三维分布曲线 ,所得到的模拟结果和理论研究结果相吻合。     

Advanced technologies for optimized sub-quarter-micrometer SOI CMOSdevices

Two manufacturable technologies of fully-depleted (FD) thin-film silicon-on-insulator (SOI) MOSFET's for low-power applications are proposed in this paper. To maintain high current drive while aggressively thinning down the SOI film, silicide is to be formed on Ge-damaged silicon layers. Ge preamorphization facilitates silicide formation at low temperature (~450°C) and effectively controls the silicide depth without void formation. It also reduces the floating body effect. In addition, a reliable gate work-function engineering is introduced for good threshold voltage management. A p⁺SiGe/Si stack gate alleviates the threshold voltage instability of SOI due to film thickness nonuniformity and broadens the design window for channel doping. These advanced technologies, compatible with existing bulk CMOS technology, are integrated into SOI CMOS process. Excellent electrical device results are presented     

Threshold voltage dependence of LOCOS-isolated thin-film SOINMOSFET on buried oxide thickness

Effects of buried oxide thickness on short-channel effect of LOCOS-isolated thin-film SOI n-MOSFETs have been investigated. Devices fabricated on SOI substrate with thin (100 nm) buried oxide have smaller roll-off of threshold voltage than those fabricated on SOI substrate with thick (400 nm) buried oxide. This is caused by a different boron concentration at the silicon film that results from the difference of stress with the buried oxide thickness. In the case of thin buried oxide, higher volumetric expansion of the field oxide causes higher stress at the interface between the silicon film and the surrounding oxide, including field and buried oxide, which prevents boron atoms from diffusing beyond the interface     

Modeling for floating body effects in fully depleted SOI MOSFETs

A model based on SOI MOSFET and BJT device theories is developed to describe the current kink and breakdown phenomena in thin-film SOI MOSFET drain-source current-voltage characteristics operated in strong inversion. The modulation of MOSFET current by raised floating body potential is discussed to provide an insight for understanding the suppression of current kink in fully depleted thin-film SOI devices. The proposed analytical model successfully simulates the drain current-voltage characteristics of thin-film SOI n-MOSFETs fabricated on SIMOX wafers     

Comparison of hole mobility in LOCOS-isolated thin-film SOIp-channel MOSFET's fabricated on various SOI substrates

The hole mobility of LOCOS-isolated thin-film silicon-on-insulator (SOI) p-channel MOSFET's fabricated on SOI substrates with different buried oxide thickness has been investigated. Two types of SOI wafers are used as a substrate: (1) SIMOX wafer with 100-nm buried oxide and (2) bonded SOI wafer with 100-nm buried oxide. Thin-film SOI p-MOSFET's fabricated on SIMOX wafer have hole mobility that is about 10% higher than that on bonded SOI wafer. This is caused by the difference in the stress under which the silicon film is after gate oxidation process. This increased hole mobility leads to the improved propagation delay time by about 10%