Simulated turn-off of 4H-SiC gate turn-off thyristors with gateelectrodes on the p-base or the n-base

Turn-off simulations of a 4H-SiC GTO thyristor structure having a gated p-base and p-type substrate are compared with that having a gated n-base and n-type substrate. Two gate drive circuits are considered, one with a voltage source and resistor between the gate and adjacent emitter region, and the other with a voltage source and resistor between the gate and farthest emitter region. The gated n-base thyristor's substrate current increases atypically before the device turns off. Also, the gated n-base structure turns off when the gate circuit is connected directly to the emitter region furthest from the gate region, but the gated p-base structure does not. Furthermore, turn-off gain is lower for the gated n-base structure due to mobility differences as demonstrated by current-voltage (I-V) and current versus time (I-t) curves     

A novel emitter-sharpened double-gate race-track-shaped fieldemitter structure

In this paper, a new emitter-sharpened double-gate race-track-shaped field emitter structure is reported. The race-track-shaped edge emission with double-gate control is used to provide high uniformity FEAs over a large area without the need of expensive submicron technology. In order to minimize the gate current, which is detrimental to the field emitter performance, an emitter-sharpened structure is used. Experimental results show that the turn-on voltage of the emitter-sharpened double-gate structure is 45 V, which is 60% smaller than that of the single-gate structure (110 V). Furthermore, the gate current of the emitter-sharpened double-gate structure is 7 times and 15 times smaller than that of the nonemitter-sharpened double-gate structure and the single-gate structure, respectively     

An advanced PSA technology for high-speed bipolar LSI

An advanced method for polysilicon self-aligned (PSA) bipolar LSI technology has realized a miniaturized transistor for high performance. By introducing the overlapping structure for double polysilicon electrodes, the emitter area is reduced to 1 µm × 3 µm and the base junction is reduced to 0.3 µm. The CML integrated circuit composed of this transistor has achieved a minimum propagation delay time of 0.29 ns/gate with power dissipation of 1.48 mW/gate. Compared to the conventional PSA method, this technology promises to fabricate higher speed and higher density LSI's.     

An Advanced PSA Technology for High-Speed Bipolar LSI

An advanced method for polysilicon self-aligned (PSA) bipolar LSI technology has realized a miniaturized transistor for high performance. By introducing the overlapping structure for double poly-silicon electrodes, the emitter area is reduced to 1/spl mu/m X 3 /spl mu/m and the base junction is reduced to 0.3 /spl mu/m. The CML integrated circuit composed of this transistor has achieved a minimum propagation delay time of 0.29 ns/gate with power dissipation of 1.48 mW/gate. Compared to the conventional PSA method, this technology promises to fabricate higher speed and higher density LSI's.     

超高速双层多晶硅发射极晶体管及电路

报道了双层多晶硅发射极超高速晶体管及电路的工艺研究．这种结构是在单层多晶硅发射极晶体管工艺基础上进行了多项改进,主要集中在第一层多晶硅的垂直刻蚀和基区、发射区之间的氧化硅、氮化硅复合介质的L型侧墙形成技术方面,它有效地减小了器件的基区面积．测试结果表明,晶体管有良好的交直流特性．在发射区面积为3μm×8μm时,晶体管的截止频率为6.1GHz．19级环振平均门延迟小于40ps,硅微波静态二分频器的工作频率为3.2GHz．     

SiGe drift base bipolar transistor with self-aligned selectiveCVD-tungsten electrodes

A new device and process technology is developed for high-speed SiGe epitaxial base transistors. A 60-nm SiGe epitaxial base and the selectively ion-implanted collector (SIC) structure enhance the cutoff frequency to about 40 GHz. Base resistance is minimized to 165 Ω (emitter area: 0.2×3 μm²), and an f_MAX of 37.1 GHz is achieved by employing 0.2-μm EB lithography for the emitter window, selective CVD tungsten for the base electrode and a self-aligned oxide side wall for the emitter-to-base separation. Circuit simulations predict that this device could reduce the ECL gate delay to below 20 ps     

Very-high-speed silicon bipolar transistors with in-situ dopedpolysilicon emitter and rapid vapor-phase doping base

We present a detailed study of the performance of very-high-speed silicon bipolar transistors with ultra-shallow junctions formed by thermal diffusion. Devices are fabricated with double-polysilicon self-aligned bipolar technology with U-groove isolation on directly bonded SOI wafers to reduce the parasitic capacitances. Very thin and low resistivity bases are obtained by rapid vapor-phase doping (RVD), which is a vapor diffusion technique using a source gas of B₂H₆. Very shallow emitters are formed by in-situ phosphorus doped polysilicon (IDP) emitter technology with rapid thermal annealing (RTA). In IDP emitter technology, the emitters are formed by diffusion from the in-situ phosphorus doped amorphous silicon layer. Fabricated transistors are found to have ideal I-V characteristics, large current gain and low emitter resistance for a small emitter. Furthermore, a minimum ECL gate delay time of 15 ps is achieved using these key techniques. Analyses of the high performance using circuit and device simulations indicate that the most effective delay components of an ECL gate are cut-off frequency and base resistance. A high cut-off frequency is achieved by reducing the base width and active collector region. In this study, RVD is used to achieve both high cut-off frequency and low base resistance at the same time     

一种单层多晶硅BiCMOS工艺研究

介绍了一种单层多晶硅ＣＭＯＳ工艺。该工艺采用Ｐ型衬底,Ｎ型Ｐ型双埋层,Ｎ型薄外延结构,掺杂多晶硅作为ＣＭＯＳ晶体管栅极和双极ＮＰＮ晶体管的发射极。ＣＭＯＳ晶体管采用源漏自对准结构,钛和铝双层金属作为元件互连线,ＰＥＣＶＤＳｉＮｘ介质作为钝化薄膜。     

场发射结构的有限元模拟

采用ANSYS有限元计算程序，对场致发射体进行模拟计算，初步研究了发射体的几何形状尺寸与其发射特性之间的联系。通过对不同几何尺寸发射体的计算结果的分析，认为发射体的尖端曲率半径及栅极的开口直径是影响发射体发射特性最主要的因素。依据合肥国家同步辐射实验室的LIGA深度光刻技术，给出可行的几何形状。     

New Gate CD Control Technology Using CF 4 Plasma Treatment Following HBr/O 2 Plasma Treatment Step in Gate Etch Process Using Organic BARC

A new technology of resist trimming in a gate etch process using organic bottom antireflective coating (BARC) for accurate and stable gate critical dimension (CD) control of sub-0.18-mum node technology is presented in this paper. The new method uses an in situ CF₄ plasma treatment following an HBr/O₂ plasma treatment step as a part of the gate etch process to achieve a stable gate CD. The new method controls gate CD by trimming the photo resist masking gate line by reducing the effect of etch by-products, the source of CD variation, after etching organic BARC with HBr/O₂ plasma. It shows the markedly improved gate CD capability over the conventional one using just an HBr/O₂ plasma treatment for the CD control. We confirm that this new method is very useful and effective for the accurate gate CD control for sub-0.18-mum node metal-oxide semiconductor technology     

共振隧穿三极管(RTT)———共振隧穿器件讲座(10)

在简述共振隧穿三极管(RTT)的特点、定义、分类的基础上,全面、系统地介绍了各种结构RTT的材料结构、器件结构、工作原理、制造工艺及器件性能参数等,对某些RTT还给出了其应用前景。由于RTT的器件结构种类繁多,其工作原理也存在差异。为了便于介绍,在栅型RTT中以Schottky栅RTT为重点,在复合型RTT中以发射极中含DBS的RTBT和RTD/HEMT型RTT为重点进行了较为详细的阐述。总之,栅型RTT结构比较简单,但增益和驱动能力较小;复合型RTT结构较复杂,但增益和驱动能力较大,而且易于和HBT或HEMT电路兼容。     

肖特基栅型共振隧穿晶体管的制作研究

已研制成了肖特基栅共振隧穿晶体管,在双势垒结构上蒸发铂金形成栅。通过调制准二维电子积累层的面积进而达到控制隧穿电流的目的。并对发射极正反接电压不同而出现的不同调制现象进行了分析。     

IGCT--GTO技术的最新进展

IGCT是一种基于 GTO结构、利用集成门极结构进行门极硬驱动、采用缓冲层结构及阳极透明发射极技术的新型大功率半导体开关器件 ,具有晶闸管的通态特性及晶体管的开关特性。本文将对 IGCT的开发过程、结构特点、器件特性及其应用前景等进行介绍。     

TFSOI complementary BiCMOS technology for low power applications

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 μm CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 μA is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 μW 1 GHz prescaler circuit is demonstrated using this technology     

新型亚50纳米硅栅制作技术

提出并演示了一新型的低成本亚50纳米多晶硅栅制作技术.该技术的特点是它与光刻分辨率无关,即不需要高分辨率光刻技术.纳米尺度的栅掩膜图案是由台阶侧壁图形的转移所形成.实验结果表明,该技术制成的硅栅的栅长由形成侧壁图形的薄膜之厚度所决定,大致为该厚度的75%—85%.SEM照片显示硅栅的剖面为倒梯形结构.与其它结构(如矩形或正梯形)相比,该结构有利于减少栅电阻.     

新型亚50纳米硅栅制作技术

提出并演示了一新型的低成本亚 5 0纳米多晶硅栅制作技术 .该技术的特点是它与光刻分辨率无关 ,即不需要高分辨率光刻技术 .纳米尺度的栅掩膜图案是由台阶侧壁图形的转移所形成 .实验结果表明 ,该技术制成的硅栅的栅长由形成侧壁图形的薄膜之厚度所决定 ,大致为该厚度的 75 %— 85 % .SEM照片显示硅栅的剖面为倒梯形结构 .与其它结构 (如矩形或正梯形 )相比 ,该结构有利于减少栅电阻 .     

An IGBT Gate Driver for Feed-Forward Control of Turn-on Losses and Reverse Recovery Current

This paper addresses the problem of turn on performances of an insulated gate bipolar transistor (IGBT) that works in hard switching conditions. The IGBT turn on dynamics with an inductive load is described, and corresponding IGBT turn on losses and reverse recovery current of the associated freewheeling diode are analysed. A new IGBT gate driver based on feed-forward control of the gate emitter voltage is presented in the paper. In contrast to the widely used conventional gate drivers, which have no capability for switching dynamics optimisation, the proposed gate driver provides robust and simple control and optimization of the reverse recovery current and turn on losses. The collector current slope and reverse recovery current are controlled by means of the gate emitter voltage control in feed-forward manner. In addition the collector emitter voltage slope is controlled during the voltage falling phase by means of inherent increase of the gate current. Therefore, the collector emitter voltage tail and the total turn on losses are significantly reduced. The proposed gate driver was experimentally verified and compared to a conventional gate driver, and the results are presented and discussed in the paper.     

A 30-ps Si bipolar IC using super self-aligned process technology

A new 30-ps Si bipolar IC technology has been developed by scaling down a bipolar transistor's lateral geometry and forming shallow junctions. The n-p-n transistor has a 0.35-µm-wide emitter and a 1.57-µm-wide base region fabricated using super self-aligned process technology (SST) with 1-µm rule optical lithography. The fTvalues achieved for this device are 13.7 GHz at a collector-emitter voltage of 1 V and 17.1 GHz at 3 V. Propagation delay times (fan-in = fan-out = 1) of 30 ps/gate at 1.48 mW/gate for nonthreshold logic and 50 ps/ gate at 1.46 mW/gate for low-level current mode logic have been achieved.     

An ultra-high-speed ECL-BiCMOS technology with silicon filletself-aligned contacts

We have developed a half-micron super self-aligned BiCMOS technology for high speed application. A new SIlicon Fillet self-aligned conTact (SIFT) process is integrated in this BiCMOS technology enabling high speed performances for both CMOS and ECL bipolar circuits. In this paper, we describe the process design, device characteristics and circuit performance of this BiCMOS technology. The minimum CMOS gate delay is 38 ps on 0.5 μm gate and 50 ps on 0.6 μm gate ring oscillators at 5 V. Bipolar ECL gate delay is 24 ps on 0.6 μm emitter ring oscillators with collector current density of 40 kA/cm². A single phase decision circuit operating error free over 8 Gb/s and a static frequency divider operating at 13.5 GHz is demonstrated in our BiCMOS technology     

Sub-20 ps ECL circuits with high-performance super self-alignedselectively grown SiGe base (SSSB) bipolar transistors

This paper describes a high maximum frequency of oscillation f_max self-aligned SiGe-base bipolar transistor technology, based on a self-aligned selective epitaxial growth (SEG) technology including graded Ge profile in an intrinsic base and link-base engineering using a borosilicate glass (BSG) sidewall structure. The transistor is a new self-aligned transistor, which we call a Super Self-aligned Selectively grown SiGe Base (SSSB) bipolar transistor. The 1st step of the annealing (800°C, 10 min) was performed for the diffusion of boron from the BSG film, before the deposition of an emitter polysilicon film. The 2nd step of the annealing (950°C, 10 sec) of emitter drive-in was carried out, which enabled us to obtain sufficient current gain using in-situ phosphorus doped polysilicon as an emitter electrode. Sheet resistance for a link-region more than one order lower than that of the epitaxial intrinsic base was obtained after heat treatment. Base profile (boron and Ge) design, and the 2-step annealing technique have realized cut-off frequency f_T of 51 GHz and f_max of 50 GHz. ECL circuits of 19-psec gate delay have been achieved