D类音频功放的自动增益控制系统

设计实现了一种用于D类音频功率放大器中的自动增益控制系统,通过自动调整D类功放的增益,增大了D类音频功放的输入信号范围,避免了削波失真,使得D类音频功放能够在较宽信号输入范围内保持良好的总谐波失真(THD),且不影响输出功率.该集成了自动增益控制系统的2.5 W单声道D类音频功放已经采用0.5 μm CMOS工艺实现.测试表明,在电源电压5 V、功放增益18 dB、负载4 Q的条件下,访D类音频功放能够在0～2.3 Vrms的信号输入范围内保持总谐波失真加噪声(THD+N)<2%,最大输出功率2.1 W.     

基于0.8μm BCD工艺的20W×2集成D类音频功放设计

基于0.8μm BCD工艺完成了一种具有高转换效率的20W×2立体声集成音频功率放大器.该放大器可在18V电源电压下以全桥输出的方式向8Ω负载提供超过20W的功率,其转换效率可达85%以上.介绍了功率输出级、过流保护电路以及高性能轨-轨比较器的设计,并基于横向双扩散MOSFET器件结构讨论了功率输出器件寄生效应对输出电压波形失真的影响.最后给出了所设计的D类音频功率放大器的测试结果.     

基于0.8μm BCD工艺的20W×2集成D类音频功放设计

基于0.8μm BCD工艺完成了一种具有高转换效率的20W×2立体声集成音频功率放大器.该放大器可在18V电源电压下以全桥输出的方式向8Ω负载提供超过20W的功率,其转换效率可达85%以上.介绍了功率输出级、过流保护电路以及高性能轨-轨比较器的设计,并基于横向双扩散MOSFET器件结构讨论了功率输出器件寄生效应对输出电压波形失真的影响.最后给出了所设计的D类音频功率放大器的测试结果.     

新型绿色能效D类音频放大器设计应用

基于NXP Class-D类TFA9810T芯片.实现一种具有立体声功能绿色能效模拟D类功率放大器设计,该音频放大器主要由全差分输入和全桥BTL、输出结构的双通道功放和二阶巴特沃思滤波器构成.详细介绍模拟D类功放系统拓扑结构,PWM调制、输入和全桥输出、负反馈、LPF滤波器电路设计,重点探讨了死区校正、EMI抑制和PCB布局设计要素.仿真洲试表明,供电电压15 V时,功放可向两个8 Ω扬声器提供10 W×2输出功率,实际转换效率可达90%,总谐波失真小于7%,1 kHz正弦渡音频输出无交越失真,无明显EMI干扰,功放壳体相对温升25℃.     

一种高效单相电源Ⅰ类线性音频功放的设计

采用SMIC0.18μm3.3V CMOS工艺,实现了单相电源Ⅰ类线性音频功放的设计。为了提高AB类功放的效率,设计了一种新型结构的Ⅰ类线性音频功放,并理论推导了它的效率。Ⅰ类音频放大器中的电源转换器能根据输入音频信号连续调节AB类功放的功率电源电压以减小功率管上的压降。为了使单相电源下PMOS和NMOS功率管功耗同时得到优化,设计了增益变化的信号处理电路。输出级采用桥式结构,并由三级运放构成以提高线性度。测试结果表明,该功放向8Ω阻性负载提供功率在小于270mW范围内时,总谐波失真与噪声之和小于0.45%,最大效率达到70%;功率在100mW范围内时,效率比AB类提高了一倍,且测试效率曲线与理论推导吻合。     

立体声D类音频功放MAX4297

MAX4297是一种立体声D类音频功率放大器。该放大器的特点:工作电压单电源2.7~5.5V;在5V供电时,每通道输出功率可达2W,在3V供电时每通道输出功率可达0.7W;在3V供电、负载阻抗RL=32Ω、输出功率在0.2W时,效率高达90%;总谐波失真加噪声(THD N)在输出功率0.2W、负载阻抗32Ω、工作电压为5V、开关频率为125kHz时为0.3%;PWM频率可选择(125kHz到1MHz分4种);有节电关闭模式,在关闭或重新启动时无“咔哒”声;内部有1A电流限制电路及过热(145℃)保护电路;有电源低压锁存保护(低于2.2V);24管脚SSOP封装;工作温度范围-40~85℃。该功放应用…     

3W无滤波D类音频功率放大器设计

设计了一种免滤波的双通道D类音频功率放大器,该功率放大器采用双边对称三角波作为载波的PWM调制方式,有效降低功放的总谐波失真度。测试结果表明:当电源电压为5V、负载为4Ω、输入1kHz的正弦波信号、额定输出功率为3W时,总谐波失真(Total harmonic distortion,THD)为10%,输出功率为1W时总谐波失真+噪声(Total harmonic distortion+Noise,THD+N)仅为0.15%,效率高达85%。电路采用无滤波器结构,可以直接驱动扬声器,具有高效率、低静态电流与较强的抗电源干扰EMI的特点。     

大功率低THD+N的D类音频功率放大器

为了减小D类放大器,尤其是大功率D类音频放大器的总谐波失真加噪声(THD+N),提出了二阶双反馈闭环结构,有效改善了失真、电源抑制和信噪比等主要性能;通过引入前馈结构,改善了输入信号动态范围.基于CSMC 0.5 μm BCD工艺,采用该结构实现的双声道2×10 W D类音频功率放大器采用全差分结构和全桥输出,THD+N低至0.05%,PSRR可达82 dB @1 kHz,效率高于90%.     

2.5W×2立体声功率放大器

本机充分利用单片双声道立体声功率放大器集成电路 TA7230P,是一款小型的立体声功率放大器(约2.4W×2)。将它与带耳机的收音机相接,扬声器便会发出悦耳的声音。关于电路构成TA7230是用通用的立体声功放级而设计的双声道功率放大器,它具有如下特点:当电源电压为14V,负荷为8Ω,失真系数为10%时,每个声道可得到2.4W 的输出。外接元件极少,最少只接7个电容。内装电源启动冲击声防止电路。IC 工作电压范围宽,Vcc=5.5V～20V。     

SSM2380：D类立体声音频放大方案

ADI公司的SSM2380是一个全集成、高效率、立体声D类音频放大器,可优化移动电话的性能。该应用电路需要很少的外部组件,工作在2.5V到5.5V单电压源下。它能够在总谐波失真（THD＋N）小于1%的前提下,持续输出2W功率,利用5.0V电压驱动一个4Ω的负载。     

A high efficiency PWM CMOS class-D audio power amplifier

Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5 μm CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD+N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 μA. The active area of the class-D audio power amplifier is about 1.47 × 1.52 mm2. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.     

An integrated 200-W class-D audio amplifier

An integrated stereo class-D audio power amplifier realized in a silicon-on-insulator (SOI)-based BCD technology is presented. The amplifier is capable of delivering 2/spl times/100 W in two 4-/spl Omega/ loads at a supply voltage of 60 V. A second-order feedback loop is used to suppress supply ripple and pulse-shape errors in the switching power stage. The limiting factor in the performance of any class-D amplifiers is the quality of the switching power stage. A high-speed low-current levelshifter and a robust deadtime control arrangement are proposed that enable the realization of a robust high-quality switching power stage. Some practical issues with respect to robustness and electromagnetic compatibility are discussed.     

CMOS PWM D类音频功率放大器的过流保护电路

基于Class-D音频功率放大器的应用,采用失调比较器及单边迟滞技术,提出了一种过流保护电路,其核心为两个CMOS失调比较器。整个电路基于CSMC0.5μmCMOS工艺的BSIM3V3Spice典型模型,采用Hspice对比较器的特性进行了仿真。失调比较器的直流开环增益约为95dB,失调电压分别为0.25V和0.286V。仿真和测试结果显示,当音频放大器输出短路或输出短接电源时,过流保护电路都能正常启动,保证音频放大器不会受到损坏,能完全满足D类音频放大器的设计要求。过流保护电路有效面积为291μm×59.5μm。     

Carrier Distortion in Hysteretic Self-Oscillating Class-D Audio Power Amplifiers: Analysis and Optimization

An important distortion mechanism in hysteretic self-oscillating (SO) class-D (switch mode) power amplifiers-carrier distortion-is analyzed and an optimization method is proposed. This mechanism is an issue in any power amplifier application where a high degree of proportionality between input and output is required, such as in audio power amplifiers or xDSL drivers. From an average-mode point of view, carrier distortion is shown to be caused by nonlinear variation of the hysteretic comparator input average voltage with the output average voltage. This easily causes total harmonic distortion figures in excess of 0.1-0.2%, inadequate for high-quality audio applications. Carrier distortion is shown to be minimized when the feedback system is designed to provide a triangular carrier (sliding) signal at the input of a hysteretic comparator. The proposed optimization method is experimentally proven in an audio power amplifier leading to THD figures that are comparable to the state of the art. Experimental hardware is a hysteretic SO bandpass current-mode-controlled single-ended audio power amplifier capable of 45 W into 8 Omega or 80 W into 4Omega from a plusmn34 V supply with less than 0.03% THD from 100 Hz to 6.7 kHz. Carrier distortion is shown to account for this limitation in THD performance.     

A THD-reduction high-efficiency audio amplifier using inverter-based OTAs with filter-output feedback

This paper presents an integrated low-voltage THD-reduction high-efficiency class-D audio amplifier using inverter-based operational transconductance amplifiers (OTAs). We propose a negative feedback loop which can compensate for external perturbations and improving output precision. The compensator increases the audio-frequency loop gain, and leads to a better rejection of audio-frequency disturbances. The use of inverter-based OTA and comparator provides low-voltage operation and low-power dissipation. The audio amplifier operates with a 1.5 V supply voltage with maximum power efficiency of 90%. The proposed class-D amplifier was implemented using a TSMC 0.18-μm 1P6M CMOS process, and the active chip area is 1.87 mm².     

A 280 mW, 0.07% THD+N class-D audio amplifier using a frequency-domain quantizer

Pulse density modulation (PDM) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in pulse width modulation based amplifiers. However, their low-voltage analog implementations also require a linear loop filter and a quantizer. A PDM based class-D audio amplifier using a frequency-domain quantization is presented. The digital intensive frequency-domain approach achieves high linearity under low supply regimes. An analog comparator and a single-bit quantizer are replaced with a current controlled oscillator (ICO) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, single-bit, class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18???m CMOS process with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-?? loudspeaker load. The amplifier can deliver the output power of 280 mW.     

计算机有源音箱的设计

就计算机有源音箱电路的设计,分别介绍了双电源电路、双声道立体声电路、超重低音电路以及静噪和保护电路的设计方法.提出了若干设计理念:如电源设计中采用简单串联武稳压,提高了设计的灵活性;双声道立体声前置采用反相放大形式,可有效减小噪声,提高信噪比;超重低音电路采用独有的高低通滤波器进行分频,可有效减小低频噪声,使超重低音浑...     

A 2.2-V operation, 2.4-GHz single-chip GaAs MMIC transceiver forwireless applications

A 2.2-V operation, single-chip GaAs MMIC transceiver has been successfully developed for 2.4-GHz-band wireless applications such as wireless local area network terminals. The chip is fabricated using a planar self-aligned gate field-effect transistor. To generate sufficient negative voltage for gate-biasing and to enhance switch power handling capability under a 2.2-V supply, a newly designed negative voltage generator with a voltage doubler (NVG-VD) and a switch control logic circuit are integrated on the chip, together with a power amplifier, a transmit/receive switch, and a low-noise amplifier. The NVG-VD is designed to produce both a 3.3-V positive step-up voltage and a -2.1-V negative voltage under 2.2 V in operation voltage. Biased with these outputs, the logic circuit accommodates high power outputs of over 25 dBm with a low operating voltage of 2.2 V in transmit mode, With a 2.45-GHz modulated signal based on IS-95 standards, a 21-dBm output power and a 33% efficiency are obtained at a ±1.25-MHz-offset adjacent channel power rejection of -45 dBc. In receive mode, a low-noise amplifier achieves a 1.8-dB noise figure and an 11-dB gain with a 3.0-mA current. This transceiver enables significant size and weight reductions in 2.4-GHz-band wireless application terminals     

Boost bridge amplifier

A novel boost bridge amplifier which inherently doubles the power supply voltage, thus providing up to four times higher peak output power than a comparable state-of-the-art class-D amplifier, is proposed. The efficiency and the total harmonic distortion of both amplifiers during the amplification of a music signal are shown to be similar     

A 64K/spl times/1 bit dynamic ED-MOS RAM

A 64K/spl times/1 bit dynamic RAM based on an innovative short channel ED-MOS process technology and an improved ED-MOS sense amplifier circuit has been realized. The RAM has been designed by using 2-3 /spl mu/m design rules and employing ED-MOS peripheral circuits capable of low supply voltage operation. As a result, dynamic memory operation has been demonstrated with an access time less than 140 ns and a cycle time of 350 ns, using a single 5 V power supply.