An accurate method of determining MOSFET gate overlap capacitance

A new method to determine gate overlap capacitance from measurements in the inversion regime of MOSFET operation is reported. Measured overlap capacitance, for submicron LDD devices, using the new method is compared with the conventional method of determining overlap capacitance from accumulation and with the reverse-biased source/drain junction method. Since transistors are rarely in accumulation during the normal operation of digital circuits, the traditional method of overlap capacitance extraction in accumulation is inappropriate. Many digital circuits operate primarily in inversion; using our new method these circuits can be modeled more accurately.     

Displacement current sensor for contact and intermittent contact scanning capacitance microscopy

In this study a displacement current capacitance sensor (DCCS) for scanning capacitance microscopy (SCM) is introduced. It can be used for both intermittent contact (IC) and contact-SCM operation. Based on I/V conversion and subsequent lock-in amplification a displacement current can be detected and used as a measure for dopant concentration. Therefore a periodic variation of the AFM tip substrate capacitance is required. This can be achieved either by a periodic tip oscillation (IC-SCM) or an applied AC voltage between tip and sample (contact-SCM). The advantage of the DCCS is the linearity, which makes it possible to detect absolute dopant concentrations.     

Scaling the Si MOSFET: from bulk to SOI to bulk

Scaling the Si MOSFET is reconsidered. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer regime, leading to an undesirably large junction capacitance and degraded mobility. By studying the scaling of fully depleted SOI devices, the important concept of controlling horizontal leakage through vertical structures is highlighted. Several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design. The concept of vertical doping engineering can also be realized in bulk Si to obtain good subthreshold characteristics without large junction capacitance or heavy channel doping     

Effects of measurement frequency and temperature anneal on differential gate capacitance spectra observed in hot carrier stressed MOSFET's

Hot carrier generated fixed and interface traps, located at the Si-SiO/sub 2/ interface near the drain junction, are observed from the gate-to-drain capacitance of the MOS transistor, using an AC measurement signal applied to the drain. When the channel is biased in inversion, the drain junction is forward biased and carriers from the AC signal source are readily injected into the channel, leading to charge exchange between the inversion carriers and the traps located in one half of the band gap. In channel depletion, the drain junction is reverse biased, and charge exchange is between the substrate majority carriers and traps located in the other half of the band gap. The charge interaction manifests itself in a differential gate capacitance, extracted from pre- and post-stress gate capacitance voltage curves. The differential capacitance spectrum shows two distinct peaks, which are attributed to the response of donor and acceptor interface traps, located on either half of the band gap. This model is supported by capacitance measurements at different frequencies. Lower frequencies lead to a proportionally larger increase in the depletion regime response. Prolonged stress results in the convolution of the two peaks. A reverse bias on the drain leads to the deconvolution of the spectrum, allowing the two peaks to be clearly resolved. Trap response may be masked by the fixed charge, but this can be overcome by depopulation of trapped electrons or neutralization of trapped holes through elevated temperature anneal. The differential gate-to-drain capacitance allows the electrical identification of both donor and acceptor interface traps in the same device.<>     

Interpretation for homojunctions of the difference between the theoretical and the experimental built-in potential determined from capacitance measurements, using interface states

The built-in voltage of a junction can be calculated theoretically and determined experimentally from capacitance measurements. The difference that is always found between these two values cannot be completely interpreted by taking into account the contribution to the capacitance of the free carriers. The remaining difference can be explained by assuming the existence of interface states in the vicinity of the junction. Formulas for the depletion-layer capacitance of abrupt and linearly graded junctions with interface states are derived. Experimental data are interpreted in relation to this model.     

Improving the accuracy and efficiency of junction capacitance characterization: strategies for probing configuration and data set size

In this paper, the on-wafer measurement of junction depletion capacitance is examined. This work provides an in-depth discussion of possible probing configurations which can be used. It outlines a method to consistently measure the junction capacitances accurately. The results from this method compare favorably with those extracted using S-parameter measurements. Additionally, methods are formulated to reduce the number of data points required for parameter extraction while at the same time maintaining a high model accuracy.     

An improved junction capacitance model for junction field-effect transistors

A new junction capacitance model for the four-terminal junction field-effect transistor (JFET) is presented. With a single expression, the model, which is valid for different temperatures and a wide range of bias conditions, describes correctly the JFET junction capacitance behavior and capacitance drop-off phenomenon. The model has been verified using experimental data measured at Texas Instruments.     

Frequency dependence of the reverse-biased capacitance of gold-doped silicon P+N step junctions

The experimentally observed frequency dependences of the reverse-biased capacitance of gold-doped silicon step junctions over the frequency range from 10 cps to 30 Mc are found to be in agreement with a simple physical model which takes into account the charge condition and the charging and discharging time constant of the deep-gold acceptor level in the transition region of the junction. Analysis based on the simple physical model provides explicit theoretical formulas for the junction capacitance at low- and high-frequency limits which show that the high-frequency capacitance under reverse bias is approximately proportional tosqrt{N_{D} - N_{Au}}and is considerably reduced below the low frequency or dc capacitance if the donors are nearly compensated by the gold. The frequency effect is important for deep energy level impurities and becomes negligible if the impurity level is at or near the band edges. The presence of gold, however, has negligible effect on the avalanche breakdown voltage ifN_{Au} < N_{D}.     

Forward-voltage capacitance and thickness of p-n junction space-charge regions

A comprehensive analytical model for the quasi-static capacitance of the space-charge region of p-n junction devices is presented. It describes the capacitance for all voltages, including voltages large enough to cause the junction barrier to vanish. The model applies for exponential-constant doping profiles, the limiting cases of which are the step and the linear-graded profiles. In addition to the analytical model, an iterative technique is developed to yield numerically the thickness of the space-charge region as a function of voltage. The capacitance model shows good agreement when compared with measured dependencies, With an empirical model for circuit simulation, and with models based on device simulation. The model extends previous replacements of the depletion capacitance, provides a tool for circuit simulation, and is intended to provide understanding of the physics related to storage of mobile holes and electrons in the junction space-charge region.     

Large signal modeling of HBT's including self-heating and transittime effects

A physically based, large signal heterojunction bipolar transistor (HBT) model is presented to account for the time dependence of the base, collector, and emitter charging currents, as well as self heating effects. The model tracks device performance over eight decades of current. The model can be used as the basis of SPICE modeling approximations, and to this end, examples are presented. A thesis for the divergence of high frequency large signal SPICE simulations from measured data is formulated, including a requisite empirical equation for the base-collector junction capacitance     

Automatic full quantum analysis of CV measurements for bulk and SOI devices

We propose a new automatic method for analysing capacitance versus voltage measurement of metal-oxide-semiconductor (MOS) devices. Based on a quantum simulation of the semiconductor capacitance, this method allows the extraction of the flat band voltage and equivalent oxide thickness even if only a small part of the measurement is relevant. This is a strong advantage for analysing different capacitances in one time, as well as dealing with high interface states densities. Moreover, this method can be applied in accumulation regime as well as in inversion regime. It is consequently a good solution to deal with SOI devices.     

激光二极管正向电特性的精确检测

采用正向交流特性结合I-V特性的方法,检测了激光二极管的串联电阻、理想因子、结电压和结电容与外加电压或电流的关系.首次发现,激光二极管的结电压、串联电阻、理想因子和结电容在阈值附近同时出现了明显的阶跃,之后结电压呈现饱和.此外还观察到,在较低的测试频率和较大的正向电压下,激光二极管的结电容具有负值.     

Space-charge layer capacitance and offset voltage of an exponential-constant p-n junction

It is important to study an exponential-constant p-n junction because it gives a realistic approximation for many diffused p-n junction profiles. To calculate the space-charge layer capacitance for this junction we use an abrupt space-charge edge approximation with a correction which includes the effect of the mobile carriers at the edges of the space-charge region. In this approach the offset voltage v_off is used in place of the built-in potential as obtained from the depletion approximation. An analytical model for the space-charge region capacitance for an exponential-constant junction is developed. This model holds well for zero bias, for small forward voltages, and for reverse voltages. It shows good agreement when compared with the Chawla-Gummel model. It is simple and gives a direct relationship between the depletion capacitance and the applied voltage.     

Development of mathematical models of semiconductor devices for computer-aided circuit analysis

This paper describes the development and verification of mathematical models which will approximate the electrical characteristics of Zener and/or avalanche diodes and tunnel diodes. Each model consists of a circuit of discrete components with their defining equations. The equations are in a form compatible with the digital computer language which makes the models useful in analysis and design, by computer, of electronic circuits containing these devices. The Zener diode model is basically the familiar Ebers-Moll conventional diode model except that additional current sources have been added to approximate the voltage regulation when breakdown of the junction occurs. The equation for junction capacitance has been modified to model the decrease in capacitance due to avalanche in the junction. A tunnel diode model is presented which approximates the entire static characteristic, including the negative resistance region. Methods for extracting model parameters from a limited number of easily obtainable data points are developed. A method for measuring and describing junction capacitance is also presented.     

Diagnostics of the models of the diode barrier capacitance

The model characteristics of the barrier capacitance of the p-n junction at an arbitrary distribution of impurities in the base are studied. It is demonstrated that the simulation of the C-V characteristic of the nonlinear capacitance can be supplemented with the analysis of its first two derivatives. The identification of the model parameters using the least-squares method is considered.     

Dynamic Processes in Sandwich Polymer Light‐Emitting Electrochemical Cells

The operational mechanism of polymer light‐emitting electrochemical cells (LECs) in sandwich geometry is studied by admittance spectroscopy in combination with numerical modeling. At bias voltages below the bandgap of the semiconducting polymer, this allows the determination of the dielectric constant of the active layer, the conductivity of mobile ions, and the thickness of the electric double layers. At bias voltages above the bandgap, p–n junction formation gives rise to an increase in capacitance at intermediate frequencies (≈10 kHz). The time and voltage dependence of this junction are successfully studied and modeled. It is shown that impedance measurements cannot be used to determine the junction width. Instead, the capacitance at intermediate biases corresponds to a low‐conductivity region that can be significantly wider than the recombination zone. Finally, the long settling time of sandwich polymer LECs is shown to be due to a slow process of dissociation of salt molecules that continues after the light‐emitting p–n junction has formed. This implies that in order to significantly decrease the response‐time of LECs an electrolyte/salt combination with a minimal ion binding energy must be used.     

集成化平面肖特基变容管微波C-V特性物理模型

提出一种集成化平面肖特基变容管微波频段 C- V特性物理模型 ,该模型考虑了由平面结构引起的分布有源层串联电阻、分布结电容、结反向饱和漏电流及侧壁电容对微波频段 C- V特性的影响 ,揭示了集成化平面肖特基变容管 C- V特性对频率的依赖 ,并对变容比作了讨论。模型与实验结果符合得很好     

Simple model for space-charge region capacitance of an exponential-constant p-n junction

Depletion layer properties have been calculated for an exponential-constant p-n junction in silicon by using a simple model. Closed-form expressions are presented for the built-in voltage V/sub bi/ and the offset voltage correction Delta V, respectively, for this junction. These formulas allow the depletion capacitance to be accurately determined from a given value of applied voltage V/sub a/ by manual calculations. The results obtained can readily be extended to other semiconductor materials and other diffused p-n junctions.<>     

Avalanche breakdown effects on AlGaAs/GaAs HBT performance

The performance of heterojunction bipolar transistors operating in the avalanche breakdown regime has been evaluated. The analysis shows that AlGaAs/GaAs HBT under avalanche breakdown has higher collector-base junction capacitance, lower Early voltage, higher device noise, lower power efficiency, lower cut-off frequency, reduced device switching speed, and degraded maximum frequency of oscillation.     

An analysis for design optimization of mesh-type high-speed opticalposition sensitive devices (MEPSDs)

An analysis is given for designing high-speed optical position-sensitive devices (PSDs) with mesh-type resistive layers used for reducing the junction capacitance. For the MEPSD, reduction of the capacitance is dependent on the selection of the strip width and strip distance, and they should be selected in such a way that the diffusion time of the carriers must not dominate the response time, compared with the RC time constant of the devices. This analysis includes the effect of the surface recombination velocity on the collected current, and it can be applied to the choice of the optimal parameters for designing the MEPSD. From the results it is found that MEPSD of 5×5 cm² can be designed to operate two orders of magnitude faster than the conventional-type PSD