A 32×32-b adiabatic register file with supply clock generator

A 32×32-b adiabatic register file with one read port and one write port is designed. A four-phase clock generator is also designed to provide supply clocks for adiabatic circuits. All the word line and bit line charge on the capacitive interconnections is recovered to save energy. Adiabatic circuits are based on efficient charge recovery logic (ECRL) and are integrated using 0.8 μm complimentary metal-oxide-semiconductor (CMOS) technology. Measurement results show that power consumption of the core is significantly reduced by a factor of up to 3.5 compared with a conventional circuit     

An efficient charge recovery logic circuit

Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows four to six times power reduction with a practical loading and operation frequency range. An inductor-based supply clock generation circuit is proposed. Circuits are designed using 1.0-μm CMOS technology with a reduced threshold voltage of 0.2 V     

基于绝热逻辑的低功耗乘法器电路设计

基于绝热开关理论的能量回收逻辑与传统的静态CMOS逻辑相比,能够大大减少电路的功率消耗。这里介绍了一种使用单相正弦电源时钟的能量回收逻辑,分别用静态CMOS逻辑和这种能量回收逻辑设计,并仿真了一个两位乘法器电路,比较了这两种电路的性能。研究表明,采用能量回收逻辑设计的乘法器显著降低了电路的功率消耗。     

The design and implementation of a low-power clock-poweredmicroprocessor

We describe the design and implementation of a 16-bit clock-powered microprocessor that dissipates only 2.9 mW at 15.8 MHz based on laboratory measurements. Clock-powered logic (CPL) has been developed as a new approach for designing and building low-power VLSI systems that exploit the benefits of supply-voltage-scaled static CMOS and energy-recovery CMOS techniques. In CPL, the clock signals are a source of ac power for the other large on-chip capacitive loads. Clock amplitude and waveform shape combine to reduce power. By exploiting energy recovery and an energy-conserving clock driver, it is possible to build ultra-low-power CMOS processors with this approach. We compare the CPL approach with a conventional, fully dissipative approach for a processor with a similar ISA and VLSI architecture which was designed using the same set of VLSI CAD tools. The simulation results indicate that the CPL microprocessor would dissipate 40% less power than the conventional design     

Power Consumption of Asymptotically Adiabatic Static Logic Gates

A computer simulation is conducted of power consumption in the 1n–1p type of asymptotically adiabatic static logic gate. The increase is estimated in dissipation due to violation of any single condition of thermodynamic reversibility. The dissipation characteristics obtained are compared with those of quasi-adiabatic gates of the 2n–2n2p and the efficient charge-recovery logic (ECRL) type.     

A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessorfor multimedia applications

We have designed a microprocessor that is based on a single instruction multiple data stream (SIMD) architecture. It features a two-way superscalar architecture for multimedia embedded systems that need to support especially MPEG2 video decoding/encoding and 3DCG image processing. This microprocessor meets all requirements of embedded systems, including (a) MPEG2 (MP@ML) decoding and graphic processing capabilities for three-dimensional images, (b) programming flexibility, and (c) low power consumption and low manufacturing cost. High performance was achieved by enhanced parallel processing capabilities while adopting a SIMD architecture and a two-way superscalar architecture. Programming flexibility was increased by providing 170 dedicated multimedia instructions. Low power consumption was achieved by utilizing advanced process technology and power-saving circuits. The processor supports a general-purpose RISC instruction set. This feature is important, as the processor will have to work as a controller of various target systems. The processor has been fabricated by 0.21-μm CMOS four-metal technology on a 9.84×10.12 mm die. It performs 2.16 GOPS/720 MFLOPS at an operating frequency of 180 MHz, with a power consumption of 1.2 W and a power supply of 1.8 V     

Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator

We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator （PCG） at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of the PCG is extensively carried out under the variations of supply voltage, process comer and the driver transistor＇s width. We propose an energy-efficient singe cycle control circuit based on the two-stage comparator for the synchronous charge recovery sinusoidal power clock generator （PCG）. The proposed PCG is used to drive the 4-bit adiabatic Ripple Carry Adder （RCA） and their simulation results are compared with the adiabatic RCA driven by the reported PCG. We have also simulated the logically equivalent static CMOS RCA circuit to compare the energy saving of adiabatic and non-adiabatic logic circuits. In the clock frequency range from 25 MHz to 1GHz, the proposed PCG gives a maximum conversion efficiency of 56.48%. This research work shows how the design of an efficient PCG increases the energy saving of adiabatic logic.     

Flexible Prime‐Field Genus 2 Hyperelliptic Curve Cryptography Processor with Low Power Consumption and Uniform Power Draw

This paper presents an energy‐efficient (low power) prime‐field hyperelliptic curve cryptography (HECC) processor with uniform power draw. The HECC processor performs divisor scalar multiplication on the Jacobian of genus 2 hyperelliptic curves defined over prime fields for arbitrary field and curve parameters. It supports the most frequent case of divisor doubling and addition. The optimized implementation, which is synthesized in a 0.13 μm standard CMOS technology, performs an 81‐bit divisor multiplication in 503 ms consuming only 6.55 μJ of energy (average power consumption is 12.76 μW). In addition, we present a technique to make the power consumption of the HECC processor more uniform and lower the peaks of its power consumption.     

准静态单相能量回收逻辑

提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.     

准静态单相能量回收逻辑

提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.     

一种交叉耦合低功耗传输门绝热逻辑电路

提出了一种新的能量恢复型电路—— Transmission Gate Adiabatic Logic(TGAL)。该电路由交叉耦合的 CMOS传输门完成逻辑运算与能量恢复 ,对负载的驱动为全绝热过程。TGAL电路输出端始终处于箝位状态 ,在整个输出期不存在悬空现象并具有良好的信号传输效果。分析了 TGAL反相器的能耗 ,并与静态 CMOS电路及部分文献中绝热电路进行了比较。使用 TGAL构成门电路与时序系统的实例被演示。应用 MOSIS的0 .2 5 μm CMOS工艺参数的模拟结果表明 ,与传统 CMOS和 2 N-2 N2 P绝热电路相比 ,TGAL电路在 1 0 0 MHz工作频率时分别节省 80 %与 60 %以上的功耗。     

钟控准静态能量回收逻辑电路

钟控准静态能量回收逻辑 (clocked quasi- static energy recovery logic,CQSERL)只在输入信号导致输出状态发生变化的情况下才对电路节点充电 (或者回收 ) ,不需要在每个功率时钟周期循环充电和回收操作 ;CQSERL是单端输入输出逻辑 ,减小了电路实现代价 .设计了 4位 QSERL 串行进位加法器 (RCA)电路 ,和相应的 CMOS电路进行了功耗比较 .功率时钟为 10 MHz时 ,CQSERL 电路功耗是对应 CMOS电路的 35 % .流片实现了一个简单结构的正弦功率时钟产生电路 ,功率时钟的频率和相位与外接系统时钟相同     

嵌入式Flash CISC/DSP微处理器的研究与实现

本文研究一种新的既具有微控制器功能,又有增强DSP功能的高性能微处理器的实现架构.在统一的增强CISC指令集下,我们将基于哈佛和寄存器-寄存器结构的微处理器模块和单周期乘法/累加器、桶形移位寄存器、无开销循环及跳转硬件支持模块、硬件地址产生器等DSP功能模块以及嵌入式Flash Memory和指令队列缓冲器有机的集成起来,在统一架构下通过单核实现CISC/DSP微处理器,有效地提高了处理器的性能.该微处理器采用0.35μm CMOS工艺实现,芯片面积为25mm².在80M工作频率下,动态功耗为425mW,峰值数据处理能力可达80MIPS.该处理器核可满足片上系统(SOC)对高性能处理器的需求.     

1.5 V CMOS full-swing energy efficient logic (EEL) circuit suitablefor low-voltage and low-power VLSI applications

A 1.5 V full-swing energy efficient logic circuit is reported that is suitable for next-generation low-power VLSI applications using a low supply voltage. At 25 MHz and at 1.5 V, the power consumption of the EEL circuit is 70% of that for an ECRL circuit and 47% of that for the static circuit     

A 16-bit carry-lookahead adder using reversible energy recoverylogic for ultra-low-energy systems

In this paper, we describe an energy-efficient carry-lookahead adder using reversible energy recovery logic (RERL), which is a new dual-rail reversible adiabatic logic. We also describe an eight-phase, clocked power generator that requires an off-chip inductor. For the energy-efficient design of reversible logic, we explain how to control the overhead of reversibility with a self-energy-recovery circuit. A test chip was implemented with a 0.8 μm CMOS technology, which included two 16-bit carry-lookahead adders to allow fair comparison: an RERL one and a static CMOS one. Experimental results showed that the RERL adder had substantial advantages in energy consumption over the static CMOS one at low operating frequencies. We also confirmed that we could minimize the energy consumption in the RERL circuit by reducing the operating frequency until adiabatic and leakage losses were equal     

基于ARM的嵌入式计算机系统的低功耗设计与实现

嵌入式计算机系统被广泛应用于便携式和移动性较强的产品中,而这些产品的低功耗设计的目标是在满足用户对性能需求的前提下,尽可能降低系统的能耗,延长设备的待机时间[1].基于ARM处理器的嵌入式计算机系统主要通过低功耗微处理器选择、接口驱动电路的设计、电源供给电路设计、动态电源管理等来实现系统的低功耗.该系统已经在产品应用,系统性能稳定,功耗很小.     

A VLIW processor with reconfigurable instruction set for embedded applications

This paper describes a new architecture for embedded reconfigurable computing, based on a very-long instruction word (VLIW) processor enhanced with an additional run-time configurable datapath. The reconfigurable unit is tightly coupled with the processor, featuring an application-specific instruction-set extension. Mapping computation intensive algorithmic portions on the reconfigurable unit allows a more efficient elaboration, thus leading to an improvement in both timing performance and power consumption. A test chip has been implemented in a standard 0.18-/spl mu/m CMOS technology. The test of a signal processing algorithmic benchmark showed speedups ranging from 4.3/spl times/ to 13.5/spl times/ and energy consumption reduced up to 92%.     

A low-power microprocessor based on resonant energy

We describe AC-1, a CMOS microprocessor that derives most of its operating power from the clock signals rather than from dc supplies. Clock-powered circuit elements are selectively used to drive high-fan-out nodes. An inductor-based, all-resonant clock-power generator allows us to recover 85% of the clock-drive energy. The measured top frequency for the microprocessor was 58.8 MHz at 26.2 mW. The resulting overall decrease in dissipation ranges from four to five times at clock frequencies from 35 to 54 MHz. We also compare the performance of the processor to a reimplementation in static logic     

一种高性能指纹锁硬件平台的设计

为提高嵌入式指纹锁稳定性,降低系统功耗,减少硬件成本,设计一种基于DSP5509的指纹锁硬件平台。与传统嵌入式指纹平台相比,该系统运用AVR单片机MEGA8作为控制模块,光学CMOS图像传感器采集图像,提高稳定性减少成本;采用TI公司最低功耗、1．8V的DSP移植指纹算法,低功耗器件XC6206P332MR管理电源,降低系统功耗。根据实际硬件乎台特点,给出系统调试时需要注意的事项。实验结果显示,该系统平台面积为25mm^2,2节干电池稳定运行一个月,静态功耗低于15μA,动态功耗小于140mA     

A 400-MHz S/390 microprocessor

A microprocessor implementing IBM S/390 architecture operates in a 10+2 way system at frequencies up to 411 MHz (2.43 ns). The chip is fabricated in a 0.2-μm L_eff CMOS technology with five layers of metal and tungsten local interconnect. The chip size is 17.35 mm×17.30 mm with about 7.8 million transistors. The power supply is 2.5 V and measured power dissipation at 300 MHz is 37 W. The microprocessor features two instruction units (IUs), two fixed point units (FXUs), two floating point units (FPUs), a buffer control element (BCE) with a unified 64-KB L1 cache, and a register unit (RU). The microprocessor dispatches one instruction per cycle. The dual-instruction, fixed, and floating point units are used to check each other to increase reliability and not for improved performance. A phase-locked-loop (PLL) provides a processor clock that runs at 2× the system bus frequency. High-frequency operation was achieved through careful static circuit design and timing optimization, along with limited use of dynamic circuits for highly critical functions, and several different clocking/latching strategies for cycle time reduction. Timing-driven synthesis and placement of the control logic provided the maximum flexibility with minimum turnaround time. Extensive use of self-resetting CMOS (SRCMOS) circuits in the on-chip L1 cache provides a 2.0-ns access time and up to 500 MHz operation