一种低功耗快速起振晶体振荡器

基于CSMC0.5μm40VBCD工艺,设计了一种32.768kHz的晶体振荡器电路。通过Matlab分析振荡条件,以指导电路设计;通过自动增益控制环路,使振荡器的起振时间低至206ms;由微电流的跨导放大器实现了集成电路中的大电阻,用在反馈电阻和滤波器中;环路稳定后,振荡器核心电路的电流仅为195nA,同时,该电路还提供占空比为46%的方波输出。     

PFM开关电源集成电路的抗电磁干扰设计

针对脉冲频率调制(PFM)开关电源(SMPS)集成电路,提出了抗电磁干扰(EMI)设计的两种方法.通过采用零电流检测电路,控制开关电源集成电路中的开关金属氧化物半导体场效应晶体管(MOSFET)在第一个谷底导通,从而降低导通电流的尖峰值.通过采用恒压和恒流设计技术,使开关电源集成电路中的电压和电流得到限制,有助于降低电流纹波.采用CSMC lμm 40 V高压工艺设计了PFM开关电源集成电路SX1618,将以上两种抗电磁干扰设计方法应用在该电路的设计中,并设计了针对性的保护结构.完成SX1618整体仿真和版图设计后进行了流片和封装,并将其应用在实际的开关电源中,经测试,开关电源的抗电磁干扰能力符合标准.     

An efficient driving method for a high-voltage CMOS driver IC

An efficient driving method for a high-voltage CMOS driver integrated circuit (IC) is proposed. It utilises an auxiliary circuit to reduce the voltage across the data driver IC when its output stages change their status. The auxiliary circuit can reduce the power consumption and relieve the thermal problems of the driver ICs. Moreover, it has load adaptive characteristics. Power consumption was reduced by 46% at one dot on/off image pattern.     

High voltage output circuit using n- and n-LDMOSFET with thick gate oxide for PDP driver IC

A novel high voltage output circuit with thick-gated LDMOSFETs is proposed to reduce the chip size and to improve the switching speed for the plasma display panels (PDP) driver IC. The chip size of the PDP driver IC using the proposed output circuit is reduced by 35% with a similar falling time compared with the conventional one. The falling time of the proposed output circuit is about 2.5 times faster than that of the conventional one under the same size when the supply voltage and load capacitance are 180 V and 100 pF, respectively.     

Design and implementation of an FPGA-based control IC forAC-voltage regulation

This paper presents a field-programmable gate army (FPGA)-based control integrated circuit (IC) for controlling the pulsewidth modulation (PWM) inverters used in power conditioning systems for AC-voltage regulation. We also propose a multiple-loop control scheme for this PWM inverter control IC to achieve sinusoidal voltage regulation under large load variations. The control scheme is simple in architecture and thus facilitates realization of the proposed digital controller for the PWM inverter using the FPGA-based circuit design approach. Bit-length effect of the digital PWM inverter controller has also been examined in this paper. The designed PWM inverter control IC has been realized using a single FPGA XC4005 from Xilinx Inc., which can be used as a coprocessor with a general-purpose microprocessor in application of AC-voltage regulation. Owing to the high-speed nature of FPGA, the sampling frequency of the constructed IC can be raised up to the range that cannot be reached using a conventional digital controller based merely on microcontrollers or a digital signal processor (DSP). Experimental results show the designed PWM inverter control IC using the proposed control scheme can achieve good voltage regulation against large load variations     

一种新型低漏电ESD电源箝位电路

在到达纳米级工艺后,传统的静电放电防护(ESD)电源箝位电路的漏电对集成电路芯片的影响越来越严重。为降低漏电,设计了一种新型低漏电ESD电源箝位电路,该箝位电路通过2个最小尺寸的MOS管形成反馈来降低MOS电容两端的电压差。采用中芯国际40 nm CMOS工艺模型进行仿真,结果表明,在相同的条件下,该箝位电路的泄漏电流仅为32.59 nA,比传统箝位电路降低了2个数量级。在ESD脉冲下,该新型ESD箝位电路等效于传统电路,ESD器件有效开启。     

双极型高精度大负载电流集成电压基准源设计

设计并实现了一种基于双极型工艺的2.5V高精度大负载电流集成基准电压源电路,通过对传统带隙基准电路的改进,设计中增加了电源电压分配电路、电流反馈电路和大电流驱动电路,实现高精度大负载电流的目标.通过Cadence软件平台下的Spectre仿真器对电路的温度系数、负载调整率、噪声、交流电源纹波抑制比、负载电流、启动时间等电参数进行仿真验证,得到了初始精度±0.5%,在-40～85℃范围内温度系数小于6×10-6/℃,负载电流0～50 mA,电源电压4.5～36 V,输出为2.5 V的集成电压基准源电路.该电路采用6 μm/36 VK极型工艺生产制造,芯片面积为1.7 mm×2.1 mm,具有过热保护、过流保护和反接保护功能.     

一种新型的具有简易APFC的SPIC电路

提出了一种新型的具有简易APFC的单片SPIC电路.通过采用集成在SPIC内部的延迟电路,使有APFC电路的总线电压由600V下降为400V.在电路中,采用长沟道的NMOS管来代替大电阻以节省版图面积.在保证所需的功率因数的情况下,总线电压的下降可以直接导致功率开关器件的比导通电阻下降,减小功率器件的损耗,提高电路的效率.同时,总线电压下降,也使电路成本降低.此外,还同时设计了相应的高压过压保护电路.理论分析与模拟结果都证明该设计是正确的和有效的.     

SET logic driving capability and its enhancement in 3-D integrated SET–CMOS circuit

The driving capability of a single-electron transistor (SET) circuit is sensitive to the load and interconnects. We discuss about improving the performance of a SET logic in hybrid SET–CMOS circuit by parameter variation and circuit architecture along with its simulation results. With an intention of studying the SET logic drivability in a SET-only circuit, we examined a circuit composed of 2¹³ SET inverters with its interconnect effect in a 3-D CMOS IC. The schematic of the simulation is based on fabrication model of this large circuit along with interlayer and coupling capacitances of its metallization. The simulation results for delay, bandwidth and power validate the efficiency of a SET circuit.     

Carbon nanotubes vacuum field emission differential amplifier integrated circuits

A novel vacuum field emission differential amplifier integrated circuit (VFE diff-amp IC) utilising carbon nanotube (CNT) emitters is presented. A dual-mask microfabrication process is employed to achieve the VFE diff-amp IC by integrating identical CNT VFE transistors with built-in split gates and anodes. The pair of integrated amplifiers shows low gate turn-on voltage, large DC gain, a reasonable transconductance, and a good common-mode rejection ratio. The approach demonstrates a new way for development of temperature- and radiation-tolerant VFE integrated microelectronics.     

一种新型的具有简易APFC的SPIC电路

提出了一种新型的具有简易APFC的单片SPIC电路.通过采用集成在SPIC内部的延迟电路,使有APFC电路的总线电压由600V下降为400V.在电路中,采用长沟道的NMOS管来代替大电阻以节省版图面积.在保证所需的功率因数的情况下,总线电压的下降可以直接导致功率开关器件的比导通电阻下降,减小功率器件的损耗,提高电路的效率.同时,总线电压下降,也使电路成本降低.此外,还同时设计了相应的高压过压保护电路.理论分析与模拟结果都证明该设计是正确的和有效的.     

Design of a sensorless commutation IC for BLDC motors

This paper presents the design and realization of a sensorless commutation integrated circuit (IC) for brushless DC motors (BLDCMs) by using mixed-mode IC design methodology. The developed IC can generate accurate commutation signals for BLDCMs by using a modified back-EMF sensing scheme instead of using Hall-effect sensors. This IC can be also easily interfaced with a microcontroller or a digital signal processor (DSP) to complete the closed-loop control of a BLDCM. The developed sensorless commutation IC consists of an analog back-EMF processing circuit and a programmable digital commutation control circuit. Since the commutation control is very critical for BLDCM control, the proposed sensorless commutation IC provides a phase compensation circuit to compensate phase error due to low-pass filtering, noise, and nonideal effects of back-EMFs. By using mixed-mode IC design methodology, this IC solution requires less analog compensation circuits compared to other commercially available motor control ICs. Therefore, high maintainability and flexibility can be both achieved. The proposed sensorless commutation IC is integrated in a standard 0.35-/spl mu/m single-poly four-metal CMOS process, and the realization technique of this mixed-mode IC has been given. The proposed control scheme and developed realization techniques provide illustrative engineering procedures for the system-on-a-chip solution for advanced digital motor control. Simulation and experimental results have been carried out in verification of the proposed control scheme.     

A 40-Gbit/s superdynamic decision IC fabricated with 0.12-μmGaAs MESFET's

This paper describes a 4O-Gbit/s decision integrated circuit (IC) fabricated with 0.12-μm gate length GaAs metal-semiconductor field-effect transistors (MESFET's). A superdynamic flip-flop circuit and a wide-band amplifier were applied in order to attain 40-Gbit/s operation. A conventional static decision IC was also fabricated for comparison. The dynamic decision IC operated up to 40 Gbit/s, which is twice as fast as the conventional static decision IC. Error-free 40-Gbit/s operation is the fastest among GaAs MESFET decision IC's     

The impact of supercomputers on IC technology development and design

Very large scale integration (VLSI) has evolved at an enormous rate, progressing from hundreds of components on an integrated circuit (IC) in the 1960's to a million components on a chip in the foreseeable future. This paper reviews some of the computer-aided design (CAD) tools that are essential for VLSI technology development and circuit design and that also require large amounts of computer resources. Specifically, we describe programs for process simulation, device simulation, and circuit simulation. This paper also reviews the impact of high-performance computing facilities on the development and use of these programs at AT & T Bell Laboratories.     

Function testing of bipolar ICs and LSIs with the stroboscopic scanning electron microscope

The functional testing of individual circuits is essential for device manufacturers when integrated circuits have not satisfied design specifications. What is required for the functional testing of modern high-density and fast IC and large scale integration (LSI) circuits is a method which has a time resolution in the subnanosecond region and a spatial resolution in the submicrometer region. Furthermore, the test probe must be easy to position on the circuit, and inspection should be possible without having to remove the passivation glass oxide. The authors show that all of these requirements can be satisfied by using a scanning electron microscope (SEM) in the stroboscopic voltage contrast mode. A microcomputer-controlled SEM allows the testing of internal circuit operations with a time resolution of 0.2 ns, a spatial resolution of 0.2 /spl mu/m, and a voltage resolution of 50 mV. Application to a bipolar hex-inverter IC, a quadruple-multiplexer IC, and a 1024 bit PROM in the megahertz region is reported to demonstrate the efficiency of the system.     

A low-power GaAs front-end IC with current-reuse configurationusing 0.15-μm-gate MODFETs

We have developed a novel current-reuse configuration of a front-end integrated circuit (IC), where the current can be reused in the whole circuit blocks that are a low-noise amplifier, local amplifier, and mixer. The power dissipation of the front-end IC is reduced by the factor of three as compared to conventional front-end ICs. Excellent RF performance such as conversion gain of 30 dB and noise figure of 1.6 dB at 1.5 GHz is attained under the conditions of the supply voltage and current of 3.6 V and 3 mA, respectively     

一种基于0.18μm CMOS工艺的上电复位电路

介绍了一种采用0.18μm CMOS工艺制作的上电复位电路。为了满足低电源电压的设计要求,采用低阈值电压(约0V)NMOS管和设计的电路结构,获得了合适的复位电压点;利用反馈结构加速充电,提高了复位信号的陡峭度;利用施密特触发器,增加了电路的迟滞效果。电路全部采用MOS管设计,大大缩小了版图面积。该上电复位电路用于一种数模混合信号芯片,采用0.18μm CMOS工艺进行流片。芯片样品电路测试表明,该上电复位电路工作状态正常。     

Design of adaptive dead-time control circuit for resonant half-bridge driver

To decrease the switching loss and the dead-time effect of resonant half-bridge inverter, a novel adaptive dead-time control circuit of resonant half-bridge driver Integrated Circuit (IC) is presented. Without increasing the pin number of IC, this circuit takes a novel strategy to adaptively regulate dead time to a temperate range between high and low thresholds. The high and low thresholds are adaptive to the fall time of output signal in a half-bridge clock cycle. The IC of the designed circuit is suitable for high-voltage applications. The dead-time regulation range of this circuit achieves 0–3.5?µs. The range of temperate dead-time state is 300?ns. The failure signal of this circuit can protect the IC and peripheral power devices by regulating operation in three clock cycles. Both simulation and measurement of the proposed circuit in a half-bridge driver IC with an operating frequency at 50?kHz are presented based on the 0.5?µm 700?V BCD process. The results of simulation and measurement show that the presented circuits’ performance is perfect.     

由版图引起的CMOS ESD保护电路失效的分析

ESD保护电路已经成为CMOS集成电路不可或缺的组成部分,在当前CMOS IC特征尺寸进入深亚微米时代后,如何避免由ESD应力导致的保护电路的击穿已经成为CMOS IC设计过程中一个棘手的问题.光发射显微镜利用了IC芯片失效点所产生的显微红外发光现象可以对失效部位进行定位,结合版图分析以及微分析技术,如扫描电子显微镜SEM、聚焦离子束FIB等的应用可以揭示ESD保护电路的失效原因及其机理.通过对两个击穿失效的CMOS功率ICESD保护电路实际案例的分析和研究,提出了改进ESD保护电路版图设计的途径.     

On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS Integrated Circuits to Meet Electromagnetic Compatibility Regulation

A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. The circuit performance to detect different positive and negative fast electrical transients has been investigated by the HSPICE simulator and verified in a silicon chip. The experimental results in a 0.13-m CMOS integrated circuit (IC) have confirmed that the proposed on-chip transient detection circuit can be used to detect fast electrical transients during the system-level ESD events. The proposed transient detection circuit can be further combined with the power-on reset circuit to improve the immunity of the CMOS IC products against system-level ESD stress.