Current/voltage characteristic collapse in AlGaN/GaNheterostructure insulated gate field effect transistors at high drainbias

The authors describe the current/voltage characteristic collapse under a high drain bias in AlGaN/GaN heterostructure insulated gate field effect transistors (HIGFETs) grown on sapphire substrates. These devices exhibit a low resistance state and a high resistance state, before and after the application of a high drain voltage, respectively. At room temperature, the high resistance state persists for several seconds. The device can also be returned into the low resistance state by exposing it to optical radiation. Electron trapping in the gate insulator near the drain edge of the gate is a possible mechanism for this effect, which is similar to what has been observed in AlGaAs/GaAs HFETs at cryogenic temperatures     

Reliability investigation of AlGaN/GaN high electron mobility transistors under reverse-bias stress

Impact of reverse-bias stress on the reliability of AlGaN/GaN high electron mobility transistors was investigated in this paper. We found that inverse piezoelectric effect could induce noisy characteristics of stress current, and the “critical voltage” increased with the drain–source bias in the step-stress experiments. Although the degradation of the gate leakage current and drain-to-source leakage current are non-recoverable, the maximum output current can recover almost completely through electron de-trapping procedure after stress. The de-trapping activation energy was estimated to be 0.30 eV by the dynamic conductance technique. The surface morphology of the electrically stressed devices was investigated after removing the gate metallization by chemical etching, and no pits or cracks under the gate contact were observed.     

Device reliability study of AlGaN/GaN high electron mobility transistors under high gate and channel electric fields via low frequency noise spectroscopy

A set of different short term stress conditions are applied to AlGaN/GaN high electron mobility transistors and changes in the electronic behaviour of the gate stack and channel region are investigated by simultaneous gate and drain current low frequency noise measurements. Permanent degradation of gate current noise is observed during high gate reverse bias stress which is linked to defect creation in the gate edges. In the channel region a permanent degradation of drain noise is observed after a relatively high drain voltage stress in the ON-state. This is attributed to an increase in the trap density at the AlGaN/GaN interface under the gated part of the channel. It was found that self-heating alone does not cause any permanent degradation to the channel or gate stack. OFF-state stress also does not affect the gate stack or the channel.     

掺杂AlGaN/GaN HEMT电流崩塌效应研究

对不同掺杂浓度AlGaN/GaN HEMTs施加直流偏置应力,研究掺杂AlGaN/GaN HEMTs电流崩塌效应.实验表明,掺杂AlGaN势垒层对器件电流崩塌效应有明显的抑制作用,随着掺杂浓度增加,掺杂对电流崩塌效应的抑制作用越显著.这是因为对于掺杂AlGaN/GaN HEMT,表面态俘获电子将耗尽掺杂AlGaN层,从而能对2DEG起屏蔽作用.AlGaN体内杂质电离后留下正电荷也能进一步屏蔽表面态对沟道2DEG的影响.     

背栅应力对LOCOS隔离的SOI器件背栅阈值电压的影响

LOCOS隔离的SOI器件的性能强烈依赖于其背栅特性,而背栅应力会影响到背栅的特性。常温下在SOI器件的背栅上施加大电压并持续30秒以上可以显著改变背栅的阈值电压。这种改变是稳定的和时不变的。对NMOS加正的背栅压和对PMOS加负的背栅压都可以提高其背栅阈值电压。实验结果表明沿着硅岛的边缘有一条从源到漏的寄生漏电通道,而且将栅,源,漏接地并在背栅上加大的偏压可以强烈影响漏电通道。因此我们可以得到结论,背栅应力会影响与漏电流直接相关的背栅阈值电压。     

Low-frequency 1/f noise and persistent transients in AlGaN-GaN HFETs

Persistent photoresponse transients and low-frequency 1/f noise were measured in barrier-controlled devices such as AlGaN-GaN heterostructure field-effect transistors (HFETs). The persistent transients and 1/f noise were observed in drain and gate currents. A model describing trapping in a barrier-controlled device introduced, and the appropriate transient evolution and the noise spectra developed. Excellent agreement was obtained between the experimental measurements and the predicted temporal response and noise spectra. Finally, the correlation between drain and gate 1/f noise was measured, confirming that the same noise source (fluctuation in surface potential) is responsible to both currents.     

Effects of SiN passivation and high-electric field on AlGaN-GaN HFET degradation

The authors report on the effects of silicon nitride (SiN) surface passivation and high-electric field stress (hot electron stress) on the degradation of undoped AlGaN-GaN power HFETs. Stressed devices demonstrated a decrease in the drain current and maximum transconductance and an increase in the parasitic drain series resistance, gate leakage, and subthreshold current. The unpassivated devices showed more significant degradation than SiN passivated devices. Gate lag phenomenon was observed from unpassivated devices and removed by SiN passivation. However, SiN passivated devices also showed gate lag phenomena after high-electric field stress, which suggests possible changes in surface trap profiles occurred during high-electric field stress test.     

The impact of surface states on the DC and RF characteristics ofAlGaN/GaN HFETs

GaN based HFETs are of tremendous interest in applications requiring high power at microwave frequencies. Although excellent current-voltage (I-V) characteristics and record high output power densities at microwave frequencies have been achieved, the origin of the 2DEG and the factors limiting the output power and reliability of the devices under high power operation remain uncertain. Drain current collapse has been the major obstacle in the development of reliable high power devices. We show that the cause of current collapse is a charging up of a second virtual gate, physically located in the gate drain access region. Due to the large bias voltages present on the device during a microwave power measurement, surface states in the vicinity of the gate trap electrons, thus acting as a negatively charged virtual gate. The maximum current available from a device during a microwave power measurement is limited by the discharging of this virtual gate. Passivated devices located adjacent to unpassivated devices on the same wafer show almost no current collapse, thus demonstrating that proper surface passivation prevents the formation of the virtual gate. The possible mechanisms by which a surface passivant reduces current collapse and the factors affecting reliability and stability of such a passivant are discussed     

AlGaN/GaN HEMT中慢瞬态的数值解释

观察了AlGaN/GaN HEMT器件在短期应力后不同栅偏置下的一组漏极电流瞬态,发现瞬态的时间常数随栅偏压变化很小,据此判断这组瞬态由电子陷阱的释放引起.为了验证这个判断,采用数值仿真手段计算了上述瞬态.分别考虑了在器件中不同空间位置的电子陷阱,分析了应力和瞬态中相应的陷阱行为,对比和解释了仿真曲线与测量结果的异同.基于上述讨论,提出测量的瞬态可能是表面深陷阱和GaN层体陷阱的综合作用的结果.     

Numerical Explanation of Slow Transients in an AlGaN/GaN HEMT

观察了AlGaN/GaN HEMT器件在短期应力后不同栅偏置下的一组漏极电流瞬态,发现瞬态的时间常数随栅偏压变化很小,据此判断这组瞬态由电子陷阱的释放引起.为了验证这个判断,采用数值仿真手段计算了上述瞬态.分别考虑了在器件中不同空间位置的电子陷阱,分析了应力和瞬态中相应的陷阱行为,对比和解释了仿真曲线与测量结果的异同.基于上述讨论,提出测量的瞬态可能是表面深陷阱和GaN层体陷阱的综合作用的结果.     

Hot-carrier-induced MOSFET degradation under AC stress

The effects of gate and drain voltage waveforms on the hot-carrier-induced MOSFET degradation are studied. Drain votage transients have little effect on the degradation rate. Only the falling edge of the gate pulse in the presence of a high drain voltage enhances the degradation rate. For devices in typical inverter circuits, dc stress results together with the substrate current waveform can predict the degradation rate under ac stress for a wide range of rise and delay times.     

热载流子应力下n-MOSFET线性漏电流的退化

研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。     

An analytical drain current model for dual material engineered cylindrical/surrounded gate MOSFET

In this paper, a drain current model incorporating drain-induced barrier lowering (DIBL) has been developed for Dual Material gate Cylindrical/Surrounding gate MOSFET (DMG CGT/SGT MOSFET) and the expressions for transconductance and drain conductance have been obtained. It is shown that DMG design leads to drain current enhancement and reduced output conductance. The effectiveness of DMG design was scrutinized by comparing with single metal gate (SMG) CGT/SGT MOSFET. Moreover, the effect of technology parameters variations workfunction difference has also been presented in terms of gate bias, drain bias, transconductance and drain conductance. Results reveal that the DMG SGT/CGT devices offer superior characteristics as compared to single material gate CGT/SGT devices. A good agreement between modeled and simulated results has also been obtained thus providing the validity of proposed model.     

Hot-electron-induced degradation of conventional, minimum overlap,LDD and DDD N-channel MOSFETs

Substrate current characteristics of conventional minimum overlap, DDD (double-diffused drain), and LDD (lightly doped drain) n-channel MOSFETs with various LDD n^- doses have been studied. Threshold voltage shift, transconductance degradation, and change of substrate current for these devices after stressing were also investigated. The minimum gate/drain overlap devices had the highest substrate current and the worst hot-electron-induced degradation. The amount of gate-to-n⁺ drain overlap in LDD devices was an important factor for hot-electron effects, especially for devices with low LDD n^- doses. The injection of hot holes into gate oxide in these devices at small stressed gate voltages was observed and was clearly reflected in the change of substrate current. The device degradation of low-doped LDD n-channel MOSFETs induced by AC stress was rather severe     

Highly stable microwave performance of InP/InGaAs HIGFETs

The fabrication and microwave performance of InP/InGaAs heterojunction insulated-gate FETs (HIGFETs) using plasma-enhanced chemical vapor deposition (PECVD)-deposited SiO₂ as the gate insulator are discussed. Extrinsic transconductances as high as 240 mS/mm were obtained. Although these devices had a drain current drift of 20% under DC bias, when operated at 5 GHz they exhibited negligible drain current drift. The observation of high transconductance and stable microwave performance makes these HIGFETs ideal candidates for microwave power applications     

应力对GaN HEMT器件电流崩塌的影响

电流崩塌是目前GaN HEMT微波功率器件中最严重的问题之一,国内外都有研究,但尚无统一结论。通过实验,研究了GaN HEMT器件电流崩塌现象。研究表明,不同电应力条件下,导致漏电流崩塌和最大跨导下降的物理机制不同,在大电场应力下,主要物理机制是栅隧穿电子填充表面态;而在热电子应力下,是沟道热电子填充界面态。     

A study on current collapse in AlGaN/GaN HEMTs induced by bias stress

Drain current collapse in AlGaN/GaN HEMTs has been studied systematically by applying bias stress to the device. The collapse was suppressed by light illumination with energy smaller than the bandgap. The position dependence of the light illumination and the measurement of series source and drain resistances revealed that the collapse was caused by the surface states between the gate and drain electrodes, which captured electrons injected from the gate. The current collapse was eliminated by the passivation of the device surface with Si/sub 3/N/sub 4/ film.     

Hot-carrier effects on gate-induced-drain-leakage (GIDL) current inthin-film SOI/NMOSFET's

The gate-induced-drain-leakage (GIDL) currents in thin-film SOI/NMOSFET's have been studied before and after front-channel hot-carrier stress. Both the normal-mode stress (with the front gate biased beyond the threshold voltage and the drain biased at a high positive voltage, while the source is grounded with the back gate) and the reverse-mode stress (with the source and drain interchanged) have been investigated. The following significant changes have been observed: i) an increase of the off-state drain GIDL current after the normal-mode stress, especially in the low gate field region, and ii) a decrease of the off-state GIDL current after the reverse-mode stress, especially in the high gate field region. These changes can be attributed to the hot-carrier induced interface traps and their effects on the parasitic bipolar transistor gain in the thin-film SOI/NMOSFET     

Gate and drain currents in off-state buried-type p-channel LDDMOSFETs

The buried-type p-channel LDD MOSFETs biased at high positive gate voltage exhibit novel characteristics: (1) the ratio of the drain to gate currents is about 1×10^-3 to 5×10^-3; and (2) the gate and drain currents both are functions of only the gate voltage minus the n-well bias. Such characteristics are addressed based on the formation of the surface n ⁺ inversion layer due to the punchthrough of the buried channel to the underlying shallow p-n junction. The measured gate current is due to the Fowler-Nordheim tunneling of electrons from this inversion layer surface and the holes generated within the high-field oxide constitute the drain current. The n⁺ inversion layer surface potential is found to be equal to the n-well bias plus 0.55 V. As a result, both the oxide field and the gate and drain currents are independent of drain voltage     

Comparative study of AlGaN/GaN HEMTs robustness versus buffer design variations by applying Electroluminescence and electrical measurements

By means of step stressing tests on AlGaN/GaN HEMTs the robustness properties of devices fabricated on wafers with different buffer designs have been compared to each other (standard UID GaN buffer and UID Al_0.05Ga_0.95N back-barrier in combination with GaN channel layer). The devices with GaN buffer showed an abrupt increase of gate leakage current after reaching drain bias values in the range of 30 V while devices with Al_0.05Ga_0.95N back-barrier did not show any degradation up to 120 V drain bias. All DC-Step-Stress tests have been accompanied by Electroluminescence (EL) analysis and electrical characterization techniques before, during and after stress. It has been shown that EL at forward and reverse bias conditions can be used as an indicator of potential device degradation. Devices comprising an AlGaN back-barrier design demonstrated superior robustness.