一种改进太阳能计算器芯片二极管稳压电路设计

对于太阳能计算器,稳压电路的设计是串联三个PN结二极管以达到稳压目的。这种设计会出现以下问题:当外部光线太强时,太阳能电池板的供电电压较高,而稳压电路由于正向饱和压降过高,不能及时将高电压释放掉,会造成计算器不能正常工作。文章研究了改进二极管稳压电路的设计,通过只变更其中的一层mask(P+),将其中一个PN结二极管改为肖特基二极管,使其正向饱和压降处于一个合理的区间,并且研究了通过该变动后不同的Ti金属厚度以及不同温度对该稳压电路的影响。结果显示该种优化完全符合应用需求。     

交流瓷介电容器的生产工艺对击穿电压的影响

击穿破坏电压是交流瓷介电容器最主要的技术参数,也是最难解决的技术难题。通过不同工艺的对比实验,具体研究了产品电极结构、引线焊接工艺、包封层固化工艺和环氧树脂包封工艺对交流瓷介电容器击穿电压的影响,据此优化了生产工艺,使得系列交流瓷介电容器耐压达到了较高的水平,Y1产品交流击穿电压达7.8kV以上,Y2产品交流击穿电压达6.0kV以上。     

利用I2V 正向特性提取PN 二极管主要参数的研究

研究了利用电流－电压（I－V）正向特性提取PN结二极管参数的方法，与通常使用的PN结二极管模型不同，本文模型考虑了并联电导对电流的影响，在I－V特性曲线上读取四级（V，I）值，用牛顿法对模型方程组进行数值求解，可提取出PN结二极管的主要参数：反向饱和电流，串联电阻，发射系数以及并联电导。结果表明，该方法简便，实用。     

有机添加剂对己二酸铵/乙二醇加水体系工作电解液性能的改善

在传统磷酸盐添加剂工艺的基础上，采用聚乙烯吡咯烷酮等有机添加剂改善工作电解液的高温稳定性，提高闪火电压。通过电解液组分的优化，降低电阻率，使传统的己二酸铵／乙二醇加水体系的适用范围从－２５～＋８５℃拓宽到＋１０５℃，工作电压从４～１００Ｖ拓宽到２５０Ｖ。由于中压电解液的电阻率ρ３０℃降至２００～２５０Ω·ｃｍ，低压电解液的电阻率ρ３０℃降至５０～７０Ω·ｃｍ，也可用于高频低阻抗品。     

医院成本核算管理浅析

实验室中制备压电陶瓷需对不同尺寸和组分的试样单独进行极化,繁琐耗时且一致性差.提出并设计了一种新型极化装置,可对每个陶瓷试样施加不同的电场,同时极化多个不同材料和厚度的陶瓷试样.给出了极化夹具、加热与保温系统、绝缘与安全设施等关键核心部分的设计结果,并进行了多陶瓷试样同步极化实验,研究了装置的极化效果和陶瓷试样的最佳极化电压、饱和电压及一致性.实验结果表明,该极化装置使用方便、安全高效,且陶瓷试样同步极化性能一致性较好.     

Computer analysis of breakdown mechanism in planar power MOSFET's

Breakdown mechanism in planar power MOSFET's having high breakdown voltage is investigated. Precise electric field distribution is obtained by two-dimensional numerical analysis. This field distribution is used to optimize device structure and to predict breakdown voltage. A technique for reducing the electric field on the silicon surface by equalizing its distribution is presented.     

ZnO压敏元件雷电流冲击试验残压波形分析

研究了ZnO压敏元件在8/20 ms雷电波冲击试验时的残压波形。实验观察到残压波波前尖峰来源于所采用的放电回路触发元件——铜球间隙;在RLC回路临界点附近,随着冲击电流峰值的增大,残压波波尾从非振荡衰减过渡到大幅度的过零振荡;残压波峰值超前于电流波峰值,说明ZnO压敏元件在冲击电流作用下呈现出电感性,且放电电流越大,呈现的电感性越大;元件厚度越大,呈现的电感性也越大。     

Extrapolation of high-voltage stress measurements to low-voltageoperation for thin silicon-oxide films

Breakdown and wearout in MOS capacitors fabricated with 10 nm-thick silicon oxide films on p-type silicon are discussed. They have been stressed at high voltages. The high-voltage-stress-induced changes in the oxide properties are extrapolated to low operating voltages. The stress voltages ranged from -7.5 V to -14.5 V. The fluence during the stress was systematically varied front 2×10^-5 C/cm² to 6 C/cm² by varying the stress time at each voltage. The number of interface traps generated by the stress increased as the stress voltage and fluence increased. However, the interface trap generation rate decreased as the fluence increased. The trap generation rate at low operating voltages was very high, but because the current through the oxide was small, the total number of traps generated was low. The trap generation rate was proportional to the inverse square root of the fluence with a voltage dependence that decreased as the fluence increased. Extrapolation of the high-voltage-stress measurements to 5 V shows that easily detectable changes in the oxide properties would only occur after several years of 5 V operation. Extrapolation of charge-to-breakdown and time-to-breakdown data to 5 V operation indicates that breakdown would occur after hundreds of years of device operation     

Stabilization of space charge polarization in ion-dispersed gate dielectric layer of organic transistors by ultraviolet illumination for write-once read-many memory

In this work, a new type organic field effect transistor (OFET) based write-once read-many memory (WORM) device was developed. The device uses an ultraviolet (UV) cross-linkable matrix polymer mixed with ionic compounds to form an ion-dispersed gate dielectric layer. Under an applied gate voltage bias, migration of cations and anions in opposite directions forms space charge polarization in the gate dielectric layer, resulting in change of the electrical characteristics. It is shown that, with UV illumination to cross-link the matrix polymer, the formed space charge polarization can be stabilized. Therefore, the OFET can be operated as a WORM with the applied voltage bias to define the polarization and in turn the stored data, and the UV illumination to stabilize the stored data.     

利用半导体PN结模型分析石英玻璃的极化过程

利用半导体PN结偏置过程的理论模型,类比分析了玻璃的热及电场极化过程。理论分析表明,在热及电场极化条件下,正、负电极与玻璃分界面处的电场及电荷分布规律与其在反向、正向偏置的2个PN结处非常相似;利用PN结偏置模型,并考虑玻璃极化过程中电子的作用,修正了极化玻璃中电场分布和载流子运动方程及其边界条件,并解释了一些已有实验现象。     

Analysis of inverse E class power amplifier with finite DC feed in sub-nominal condition

In this work an inverse E power amplifier with finite DC feed in sub-nominal condition is discussed. In the conventional inverse E the DC feed inductor is considered very large which imposes some conditions to the circuit such as constant current drawn from voltage supply and also a large value for inductance is hard to implement on-chip so this work removes the very large condition from DC feed inductance and proposes a finite DC feed for the structure and extracts the circuit parameters and design equations with regards to this matter. Furthermore to achieve a flexible design this work uses the phase shift between input and output voltages to control efficiency, peak switch voltage and peak switch current then the value of circuit elements and the tradeoffs for every choice are discussed in details and a design guideline is presented for achieving different goals in a finite DC feed inverse E PA. Finally the circuit is simulated in the 0.18 µm CMOS technology and the results are being verified.     

一种低温漂输出可调带隙基准电压源的设计

带隙基准电压源是利用PN结电压的负温度系数和不同电流密度下两个PN结电压差的正温度系数电压相互补偿,而使输出电压达到很低的温度漂移。带隙电压基准具有低温度系数、高电源抑制比、低基准电压以及长期稳定性等优点。根据带隙基准电压源理论,在传统CMOS带隙电压源电路结构的基础上,采用一级温度补偿、电流反馈等技术,设计出了一种高精度、输出可调的带隙电压基准源。该电路具有精度高,输出电压可调,稳定性好,易于实现的特点。     

Software Implementation of a PN Spread Spectrum Receiver to Accommodate Dynamics

To optimize the threshold of a pseudonoise (PN) spread spectrum modem for use over an aircraft/satellite communications link at SHF, the effects of Doppler must be taken into account. Reconstitution of carrier phase by a Costas loop to coherently demodulate the PSK data and also the delay-lock error voltage has typically been the practice in PN modems intended for ground applications. To accommodate the platform dynamics, the Costas loop must have a relatively wide bandwidth, and this implies a significant threshold degradation. An alternate implementation employs a noncoherent carrier tracking loop which maintains frequency lock rather than phase lock. Now, the delay-lock error voltage is noncoherently demodulated. For the airborne application, analysis and simulations show this implementation will extend the receiver's tracking threshold significantly (up to 6 dB) for the worst case dynamics profile. An experimental project was undertaken to modify an existing ground PN modem (AN/USC-28, ADM version) for flight test. A software implementation of the digital tracking algorithms was selected where a HP-2100A minicomputer controls carrier frequency and PN code phase via digital phase shifters. The Costas demodulator for extracting PSK data resides entirely in software, and is completely segregated from PN tracking. In laboratory testing of the receiver with simulated dynamics and in actual flight tests, the demonstrated performance was found to approach closely the goals established by the analyses and simulations.     

Negative resistance in Zener diodes

The paper reports the detection of negative resistance in Zener diodes when the frequency of the applied voltage exceeds a certain critical value. The observation shows that this critical frequency, depending upon the instantaneous breakdown voltage and current level in the device, has an inverse relation with the d.c. breakdown voltage of the device.     

Spin Polarization of Carriers in InGaAs Self-Assembled Quantum Rings Inserted in GaAs-AlGaAs Resonant Tunneling Devices

In this work, we have investigated transport and polarization resolved photoluminescence (PL) of n-type GaAs-AlGaAs resonant tunneling diodes (RTDs) containing a layer of InGaAs self-assembled quantum rings (QRs) in the quantum well (QW). All measurements were performed under applied voltage, magnetic fields up to 15 T and using linearly polarized laser excitation. It was observed that the QRs’ PL intensity and the circular polarization degree (CPD) oscillate periodically with applied voltage under high magnetic fields at 2 K. Our results demonstrate an effective voltage control of the optical and spin properties of InGaAs QRs inserted into RTDs.     

Breakdown voltage of the surface glow discharge

Breakdown voltage is an important parameter of the surface glow discharge especially from the standpoint of practical applications. The experimental results of the breakdown voltage measurements for this type of discharge together with the results obtained from theoretical analysis are given. The presented model is based on the calculation of the electric field, trajectories of charged particles (which do not follow the flux lines) and finally on the testing of the condition for the self sustained discharge. The obtained theoretical results are in good agreement with the experimental ones     

新型功率器件SON-LDMOS的设计和研究

本文提出了一种新型的对称式SON LDMOS功率器件.在对器件击穿电压进行解析分析的基础上,利用Silvaco TCAD仿真软件Atals验证了漂移区设计对器件击穿电压的影响,证明了峰值击穿电压的存在.并且对比分析了SON　LD-MOS与SOI LDMOS击穿电压和寄生电容方面的优势,研究表明SON LDMOSD在击穿电压上比SOI LDMOS器件提高了近3倍,并且其寄生电容也较小,这为SON LDMOS在功率方面的应用提供了部分理论支持.     

ESD保护结构设计

静电损伤失效可能是热击穿（电流）造成的结或金属布线熔融失效,也可能是强电场（电压）诱发的介质失效,文章主要从电流热击穿方面探讨了静电触发时的ESD（Electro—Static-Discharge）保护结构的保护机理和失效机理以及工艺和版图上的应对措施。保护结构工作时的电流泄放能力决定了其保护能力,这种能力可以通过使泄放电流均匀、优化PN结特性等方面加强。电流泄放的均匀性可以在工艺版图上进行优化,结两侧浓度决定了结的耐受能力和结上的偏压,进而影响器件功耗。另外还提及了保护结构的贞面影响以及工艺上的优化方案。     

CMOS电路中抗Latch-up的保护环结构研究

闩锁是CMOS集成电路中的一种寄生效应,这种PNPN结构一旦被触发,从电源到地会产生大电流,导致整个芯片的失效。针对芯片在实际测试中发现的闩锁问题,介绍了闩锁的测试方法,并且利用软件Tsuprem4和Medici模拟整个失效过程,在对2类保护环(多子环/少子环)作用的分析,以及各种保护结构的模拟基础之上,通过对比触发电压和电流,得到一种最优的抗Latch up版图设计方法,通过进一步的流片、测试,解决了芯片中的闩锁失效问题,验证了这种结构的有效性。     

内调制光电探测器特性的模拟与实验分析

给出了内调制光电探测器受光结光生电压、输出结电流及内调制特性的理论模型;在此基础上进行数值计算,得到模拟曲线;并将实验曲线与模拟曲线对比,结果吻合.然后深入分析了栅压对受光结的光电特性的影响,以及在横向发生的抽取效应对受光结的影响,并对此器件内调制特性进行解析,阐明了其内调制工作机制.