采用多次离子注入调整亚微米CMOS电路的阈电压

采用多次离子注入来调整亚微米CMOS的NMOS和PMOS管的阈值电压是研究亚微米CMOS电路的关键.浅离子注入调节表面掺杂浓度以达到调整阈值电压的目的.深离子注入调整源漏穿通电压.与LDD、硅化物工艺相合,已研制出0.5μm的CMOS 27级环振电路,门延迟为130ps.     

2μmp阱CMOS工艺中提高源－漏穿通电压的方法

采用防穿通注入的工艺方案，对提高２μｍｐＭＯＳ管的源漏穿通电压应选用的工艺条件做了实验研究。给出了加防穿通注入工艺的实验结果及其对Ｖ＿（Ｔｐ）的影响。     

漏轻掺杂MOSFET的源漏穿通

测量和分析了1μm LDD MOSFET的穿通特性,与常规结构的MOSFET加以比较.结果表明,LDD结构能够有效地抑制DIBL效应、大幅度地提高短沟道MOSFET的源漏穿通电压.此外,还给出LDD MOSFET源漏穿通机制的定性解释.     

两次硼注入短沟道MOSFET

本文给出了用于高速逻辑电路的两次硼离子注入 n 沟增强型 MOS EFT 器件的阈值电压和电流一电压特性。衬底采用 P 型(100)15Ω cm 的高阻材料,以降低结电容和阈值衬底敏感度。用浅的硼注入来提高阈值电压,之后,再进行一次较深的离子注入,以提高源—漏之间的穿通电压。这种方案特别有利于制作短沟道器件。我们对两次离子注入的器件进行了一维分析,以估测离子注入的剂量和能量对器件阈值电压的影响,同时我们还根据器件的几何尺寸进行了准二维分析,来了解器件的短沟道效应。为了得出电流一电压特性,一维分析用于线性区,而以泊松方程解为基础的准二维分析用于夹断区,以估测空间电荷限制电流。计算结果与实验室试制器件的特性非常符合。     

1700V/100A平面型NPT-IGBT静态特性研究

基于现有工艺平台设计一款1 700V/100A非穿通型绝缘栅双极晶体管器件(Non punch through insulator gate bipolar transistor,简称NPT-IGBT),元胞采用平面型结构,元胞注入采用自对准工艺,背发射极采用透明集电极技术,对其静态特性进行工艺仿真。仿真结果显示,调整P阱注入剂量及P阱推结时间可以改变器件的阈值电压,调整P阱及背面P+集电极注入剂量可以改变器件的饱和电压。将此设计进行流片验证,结果显示击穿电压在2 100V以上,饱和压降在2.5~2.7V之间,阈值电压在3.9~5.9V之间,实测值和仿真值相差不大,在误差接受范围之内。     

n型纳米非对称DG-TFET阈值电压特性研究

n型纳米非对称双栅隧穿场效应晶体管(DG-TFET)速度快、功耗低,在高速低功耗领域具有很好的应用前景,但其阈值电压的表征及其模型与常规MOSFET不同.在深入研究n型纳米非对称DG-TFET的阈值特性基础上,通过求解器件不同区域电场、电势的方法,建立了n型纳米非对称DG-TFET器件阈值电压数值模型,探讨了器件材料物理参数以及漏源电压对阈值电压的影响,通过与Silvaco Atlas的仿真结果比较,验证了模型的正确性.研究表明,n型纳米非对称DG-TFET的阈值电压分别随着栅介质层介电常数的增加、硅层厚度的减薄以及源漏电压的减小而减小,而栅长对其阈值电压的影响有限.该研究对纳米非对称DG-TFET的设计、仿真及制造有一定的参考价值.     

一种可应用于UIRFPA的基准电压源

设计了一种基于阈值电压的基准电压源.利用与温度的平方成正比的电流对具有正负温度系数的电压相加时产生的与温度及工艺有关的特征电流进行了分析,得到了近似等于温度为0K时MOS管的阈值电压的基准电压值.基于Spectre软件的仿真结果表明,当电源电压为1.7V时,在-20～85℃的温度范围内,该基准电压源的温度系数为5.7 ...     

中压沟槽MOSFET的设计与研究

基于仿真和实验方法,开展了100VN沟槽MOSFET的设计研究工作.通过沟槽深度,体区注入剂量和栅氧化层厚度拉偏,获得了对击穿电压,阈值电压和导通电阻的影响规律并对机理进行了分析,仿真工具同时描述了器件内部的电流路径和碰撞电离率分布.随着沟槽深度增加击穿电压先升后降,导通电阻则表现为相反趋势;击穿电压与注入剂量具有弱相关性,阈值电压随注入剂量增加而升高;击穿电压随着栅氧化层厚度增加整体表现上升趋势,但变化幅度不大,阈值电压与厚度变化表现出强相关性.通过逐步优化获得了最终结构和工艺参数为沟槽深度1.5μm,体区注入剂量1.3E13,栅氧化层厚度700 A,通过流片获得器件最终电性参数为击穿电压为105.6 V,阈值电压2.67 V,导通电阻3.12 mR,相较于仿真参数分别有98%,94%和75%的变化率.     

提高E^2PROM中NMOS管源漏穿通电压的实验研究

为了提高Ｅ＾２ＰＲＯＭ中Ｎ管源漏穿通电压，用实验的方法对制造工艺进行了研究。结果表明，高能量注入是提高ＶＰＴ的有效手段，但受到ｐｎ结击穿的限制，只适用于低区短沟Ｎ管；ＤＤＤ工艺大幅度高ＶＰＴ，但ｐｎ结击穿电压低于２０Ｖ，不能应用于高压ＭＯＳ管；采用适量的防穿通注入和适当增大沟道长度为最理想的工艺途径。     

MOSFET击穿特性的二维数值模拟

0引言 MOSET中产生击穿的机构有漏源击穿和栅绝缘层击穿。其中漏源击穿电压是由漏一衬底的PN结雪崩击穿电压与穿通电压两者中的较小者决定的。本文对漏源击穿运用MEDICI二维器件模拟软件进行分析。     

基于SWB环境下的nm级NMOS虚拟优化

介绍了Synopsys Inc.推出的新一代(第五代)nm级TCAD仿真平台--Sentaurus Work-bench(SWB)的系统结构、基本功能及其优化功能,重点介绍了SWB的DOE及RSM优化机制。基于SWB环境实现了nm级NMOS集成化管芯的可制造性设计及优化。在对NMOS集成化管芯的设计过程中,围绕Vt进行了可制造性设计,利用DOE试验方法和RSM对Vt进行了优化,得到了阈值电压(Vt)和调阈值注入剂量(Vt_Dose)、能量(Vt_Energy)及抑制穿通注入剂量(PNCH_Dose)、能量(PNCH_Energy)之间的RSM响应表面关系。在此基础上,分析了Vt各影响因素与Vt之间的关系,从而指导了在Vt的设计过程中各个主要影响参数的选取。     

Anomalous narrow channel effect in trench-isolated buried-channelp-MOSFET's

An anomalous threshold voltage dependence on channel width measured on 0.25 μm groundrule trench-isolated buried-channel p-MOSFET's is reported here. As the channel width is reduced, the magnitude of the threshold voltage first decreases before the onset of the expected sharp rise in Vt for widths narrower than 0.4 μm. Modeling shows that a “boron puddle” is created near the trench bounded edge as a result of transient enhanced diffusion (TED) during the gate oxidation step. TED is governed by interstitials produced by a deep phosphorus implant, used for latchup suppression, diffusing towards the trench sidewall and top surface of the device. The presence of the “boron puddle” imposes a penalty on the off-current of narrow devices. A solution for minimizing the “boron puddle” is demonstrated with simulations, confirmed by measurements     

Reduction of threshold voltage sensitivity in SOI MOSFET's

The threshold voltage sensitivity, of fully depleted SOI MOSFET's to variations in SOI silicon film thickness was examined through both simulation and device experiments. The concept of designing the channel V_th implant to achieve a constant dose within the film, rather than a constant doping concentration, was studied for a given range of film thicknesses. Minimizing the variation in retained dose reduced the threshold voltage sensitivity to film thickness for the range of t_si examined. One-dimensional process simulations were performed to determine the optimal channel implant condition that would reduce the variation in retained dose using realistic process parameters for both NMOS and PMOS device processes. SOI NMOS transistors were fabricated. The experimental results confirmed the simulation findings and achieved a reduced threshold voltage sensitivity     

亚65nm工艺新型p结构多米诺与门设计

利用休眠晶体管、多阈值和SEFG技术(源跟随求值门技术),设计了一种新型的p结构多米诺与门.HSPICE仿真结果表明,在相同的时间延迟下,与标准双阈值多米诺与门、标准低阈值多米诺与门和SEFG结构相比,提出的新型多米诺与门的漏电流分别减小了43%,62%和67%,噪声容限分别增大了3.4%,23.6%和13.7%.从而有效地解决了亚65nm工艺下多米诺与门存在的漏电流过大,易受干扰的问题.分析并得到了不同结构的休眠多米诺与门的漏电流最低的输入矢量和时钟状态.     

Threshold voltage instability of nanoscale charge trapping non-volatile memory at steady phase

Post program/erase (P/E) cycled threshold voltage (Vt) instability is one of the major reliability concerns for nanoscale charge trapping (CT) non-volatile memory (NVM) devices. In this study, anomalous program state Vt instability of fully annealed nanoscale nitride based CT NVM device at steady phase is carefully examined. To the best knowledge of the authors, for the first time, the relationship between the derived apparent activation energy (Eaa) of this anomalous program state Vt instability at steady phase and the P/E cycle count is established. They are found to adhere to the power law decay relationship. Anomalous program state Vt instability at steady phase was found to favor lateral redistribution of trapped charge model instead of vertical charge transport model. Physical interpretations of its underlying physical mechanisms and reliability implications to reliability performance of nanoscale nitride based CT NVM were presented. Plausible technical solutions to mitigate the reliability degradation induced by this anomalous program state Vt instability on nanoscale nitride based CT NVM were proposed.     

Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits

In nanoscale CMOS circuits the random dopant fluctuations (RDF) cause significant threshold voltage (Vt) variations in transistors. In this paper, we propose a semi-analytical estimation methodology to predict the delay distribution [Mean and Standard Deviation (STD)] of logic circuits considering Vt variation in transistors. The proposed method is fast and can be used to predict delay distribution in nanoscale CMOS technologies both at the circuit and the device design phase. The method is applied to predict the delay distributions in different logic gates and flip-flops and is verified with detail Monte Carlo simulations. It is observed that a 30% spread (STD/Mean) in Vt variation results in 5% spread in the delay of logic gates (inverter, NAND, etc.). The effect of Vt variation due to RDF is more significant in the setup time (STD/Mean = 11%) and clock-to-output delay (STD/Mean = 5% to 25%) of flip-flops.     

Standby/active mode logic for sub-1-V operating ULSI memory

New gate logics, standby/active mode logic I and II, for future 1 Gb/4 Gb DRAMs and battery operated memories are proposed. The circuits realize sub-l-V supply voltage operation with a small 1-μA standby subthreshold leakage current, by allowing 1 mA leakage in the active cycle. Logic I is composed of logic gates using dual threshold voltage (Vt) transistors, and it can achieve low standby leakage by adopting high Vt transistors only to transistors which cause a standby leakage current. Logic II uses dual supply voltage lines, and reduces the standby leakage by controlling the supply voltage of transistors dissipating a standby leakage current. The gate delay of logic I is reduced by 30-37% at the supply voltage of 1.5-1.0 V, and the gate delay of logic II is reduced by 40-85% at the supply voltage of 1.5-0.8 V, as compared to that of the conventional CMOS logic     

Operational Amplifier Based Test Structure for Quantifying Transistor Threshold Voltage Variation

A new test structure has been developed, which is comprised of MOSFET arrays and an on-chip operational amplifier feedback loop for measuring threshold voltage variation. The test structure also includes an on-chip clock generator and address decoders to scan through the arrays. It can be used in an inline test environment to provide rapid assessment of Vt variation for technology development and chip manufacturing. Hardware results in a 65-nm technology are presented. The significance of the bias dependence of Vt variation is discussed for SRAM product designs.      

A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations

This paper presents a forward body-biasing (FBB) technique for active and standby leakage power reduction in cache memories. Unlike previous low-leakage SRAM approaches, we include device level optimization into the design. We utilize super high Vt (threshold voltage) devices to suppress the cache leakage power, while dynamically FBB only the selected SRAM cells for fast operation. In order to build a super high Vt device, the two-dimensional (2-D) halo doping profile was optimized considering various nanoscale leakage mechanisms. The transition latency and energy overhead associated with FBB was minimized by waking up the SRAM cells ahead of the access and exploiting the general cache access pattern. The combined device-circuit-architecture level techniques offer 64% total leakage reduction and 7.3% improvement in bit line delay compared to a previous state-of-the-art low-leakage SRAM technique. Static noise margin of the proposed SRAM cell is comparable to conventional SRAM cells.     

薄膜SOI上大于600 V LDMOS器件的研制

针对600 V以上SOI高压器件的研制需要,分析了SOI高压器件在纵向和横向上的耐压原理。通过比较提出薄膜SOI上实现高击穿电压方案,并通过仿真预言其可行性。在埋氧层为3μm,顶层硅为1.5μm的注氧键合(Simbond)SOI衬底上开发了与CMOS工艺兼容的制备流程。为实现均一的横向电场,设计了具有线性渐变掺杂60μm漂移区的LDMOS结构。为提高纵向耐压,利用场氧技术对硅膜进行了进一步减薄。流片实验的测试结果表明,器件关态击穿电压可达600 V以上(实测832 V),开态特性正常,阈值电压提取为1.9 V,计算开态电阻为50Ω.mm2。