洁净区硅外延生长及其在分立器件上的应用

<正> 一、前言近年来为了解决硅器件工艺中的重金属沾污问题,国内外开展了大量的有关吸杂的研究工作。由于内吸杂技术具有独特的优点,国外有些科学家把它称作为“硅材料的第二次工业革命”。本文主要是讨论洁净区形成的原理、工艺和以洁净化硅衬底制备硅外延材料及其在硅分立器件上的应用等方面问题。我们知道,制备集成电路所用硅片的洁净区化和外吸杂技术用以减少外延层中缺陷,提高外延层质量的研究工作,在国内外报道的比较多。然而利用洁净区化硅衬底制备优     

刻槽硅衬底上的GaAs/AlGaAs超晶格材料的微结构特性

用分子束外延在有刻槽的{001}硅衬底上生长了 GaAs/Al_(0.3)Ga_(0.7)As超晶格材料,利用横断面透射电子显微术对非平而异质结的生长行为和微观结构进行了观察.研究结果表明硅衬底上刻槽的几何形状对外延层的微缺陷特性及生长行为有一定影响,和Si{001}晶面相比,Si{113}可能是一个有利于生长半导体异质结的晶面.     

高失配半导体薄膜材料的纳米异质外延新技术

纳米异质外延技术是制备高失配半导体薄膜的一种纳米制作技术路线,随着超大规模集成电路纳米图样加工技术的进步,它将在制备无缺陷密度且单晶品质完美的高失配半导体薄膜材料中发挥巨大的作用。详细地综述了纳米异质外延技术的原理,介绍了纳米图样制作技术并展示了运用纳米异质外延技术在Si(111)衬底上实现高失配GaN(失配度为20%)薄膜材料及在Si(100)衬底上实现InP薄膜材料的高品质单晶外延生长。     

硅衬底上异质外延生长硅化钴研究进展

综述近年国内外在CoSi2／Si异质外延生长技术领域的研究进展,在半导体衬底上异质外延具有优良导电特性的金属硅化物,从基础研究和技术发展两方面都具有重要价值。利用Co／Ti／Si多层薄膜固相反应实现CoSi2／Si异质外延,是近年取得重要进展的新方法。应用这种方法在（111）和（100）硅衬底上都可实现CoSi2外延生长,无需在超高真空下进行,与硅器件基本工艺相容性好,可形成自对准硅化物接触结构,对发展新器件制造技术有重要作用。在简要介绍分子束外延和离子合成CoSi2外延薄膜生长技术后,重点介绍和评述新型固相异质外延方法的工艺技术、机理和应用研究进展。     

硅基氮化镓异质结材料与多晶金刚石集成生长研究

在50.8 mm(2英寸)硅基氮化镓异质结半导体材料上采用低压等离子体化学气相沉积方法淀积100 nm厚度的氮化硅材料,然后采用微波等离子体化学气相沉积设备在氮化硅层上方实现多晶金刚石材料的外延生长.采用氮化硅作为过渡层和保护层有效调控了材料应力,保护了氮化镓基材料在多晶外延过程中被氢等离子体刻蚀,使得外延前后氮化物异...     

MPCVD生长半导体金刚石材料的研究现状北大核心

简要介绍了半导体金刚石材料优异的电学和光学性质、主要制备方法以及采用微波等离子体化学气相沉积(MPCVD)技术在制备高质量半导体金刚石材料方面的优势。重点就MPCVD技术在半导体金刚石材料的高速率生长、大尺寸生长、高质量生长以及电学掺杂等四个方面的研究现状进行了详细总结。详细探讨了目前半导体金刚石材料在大尺寸单晶金刚石衬底制备、高质量单晶金刚石外延层生长以及金刚石电学掺杂等方面还存在的一些基本问题。指出在大面积单晶金刚石衬底还没有实现突破的情况下,半导体金刚石材料和器件结构的生长模式。     

基于图形衬底的InAs/GaAs量子点和量子环液滴外延

液滴外延生长半导体材料是一种较为新颖的MBE生长技术,而图形衬底对液滴外延的影响到目前为止并没有非常详细的研究结果. 作者在GaAs μm级别图形衬底上进行了InAs的液滴外延生长,并在不同结构的图形衬底上得到了不同的InAs量子点和量子环生长结果.基于生长结果,分析了图形衬底对液滴外延的影响和液滴外延下量子点和量子环的形成机制以及分布规律.     

蓝宝石和尖晶石上化学气相淀积硅的性质与制备

一、引言可用作硅膜外延生长村底的单晶材料已超过十种,已经发表各种衬底上硅的异质外延生长的评论文章。三年来仅只对单晶α-Al_2O_3(商业上称蓝宝石,虽然作为衬底的材料是没有过渡金属杂质的)和镁铝尖晶石进行一定的研究。本文专门对蓝宝石和尖晶石上外延硅的性质进行比较,重点是研究外延生长条件与对集成电路工艺中硅一绝缘体结构应用成兴趣的牛导体性质之间的关系。对六方晶系蓝宝石和立方晶系尖晶石上的立方晶系硅性质的比较,提     

半导体集成电路

所谓半导体集成电路,就是把在一个或一个以上的半导体衬底上制作的电路元件相互连接的电路。半导体衬底现在基本上是采用硅。此外也有用锗和以砷化镓为代表的Ⅲ—Ⅴ族金属间化合物作衬底的。在衬底上,通过扩散、外延生长、光刻、介质生长和氧化等芯片工艺制作晶体管,二极管和电阻,用pn结或介质把器件之间进行隔离。把衬底表面用介质覆盖以     

重掺磷衬底上外延层生长工艺研究

重掺磷衬底上硅外延片是制作集成电路开关电源的肖特基二极管和场控高频电力电子器件的首选产品。重掺磷衬底外延片可以大幅降低压降中半导体部分引起的压降所占的比例。介绍了重掺磷外延片的一种实用生产技术,在高浓度衬底外延后失配现象、杂质外扩抑制方法、减少外延过程中衬底磷杂质的挥发等方面进行了研究。在研究的基础上使用CSD公司的EpiPro5000型外延设备进行工艺试验,采用盖帽层分层生长、变流量赶气和低温度生长等工艺条件控制磷杂质的扩散和挥发,从而减少自掺杂效应,获得良好的电阻率均匀性和陡峭的外延层过渡区。试验结果已成功应用于大规模生产,得到了用户认可。     

硅发光研究进展

硅是间接带隙半导体, 不能有效地发光.量子理论、超晶格理论和纳米技术的发展,给硅基发光研究提供了理论的和技术的支撑.研究者通过不同的途径去实现硅的有效发光:多孔硅、纳米硅、Si/SiO2超晶格、计算化设计与硅晶格匹配的直接带隙半导体.文章报道了这些方面的最新研究进展.     

Die-attachment solutions for SiC power devices

Silicon carbide has become a very attractive material for high temperature and high power electronics applications due to its physical properties, which are different than those of conventional Si semiconductors. However, the reliability of SiC devices is limited by assembly processes comprising die attachment and interconnections technology as well as the stability of ohmic contacts at high temperatures.The investigations of die to substrate connection methods which can fulfill high temperature and high power requirements are the main focuses of the paper. This work focuses on die attach technologies: solder bonding by means of gold-germanium alloys, adhesive bonding with the use of organic and inorganic conductive compositions, as well as die bonding with the use of low temperature sintering with silver nanoparticles. The applied bonding technologies are described and obtained results are presented. Of the methods tested, the best solutions for high temperature application are two die attach technologies: silver glass die attach and die bonding with the use of low temperature sintered Ag nanopowders.     

A 1-MHz hard-switched silicon carbide DC-DC converter

Silicon Carbide (SiC) is a wide bandgap semiconductor material that offers performance improvements over Si for power semiconductors with accompanying benefits for power electronics applications that use these semiconductors. The wide bandgap of SiC results in higher junction forward voltage drops, so SiC is best suited for majority carrier devices such as field effect transistors (FETs) and Schottky diodes. The wide bandgap of SiC results in it having a high breakdown electric field, which in turn results in lower resistivity and narrower drift regions in power devices. This dramatically lowers the resistance of the drift region and means that SiC devices with substantially less area than their corresponding Si devices can be used. The lower device area reduces the capacitance of the devices enabling higher frequency operation. Here, the results from a 1-MHz hard-switched dc-dc converter employing SiC JFETs and Schottky diodes will be presented. This converter was designed to convert 270Vdc to 42Vdc such as may be needed in future electric cars. The results provide the performance obtained at 1MHz and demonstrate the feasibility of a hard-switched dc-dc converter operating at this frequency.     

Epitaxial growth on 4H-SiC by TCS as a silicon precursor

onship with the growth temperature and growth rate. Silicon droplets with different sizes are observed on the surface of the homoepitaxial layer in a low C/Si ratio of 0.32.     

High-quality oxide formed by evaporation of SiO nanopowder: Application to MOSFETs on plastic substrates and GaN epilayers

Although good gate oxide of SiO₂ is usually formed by high-temperature thermal oxidation, lowering the temperature for formation of SiO₂ is mandatory for future Si VLSIs, in particular, for flexible ICs, the demand for which has been increasing every year. Vacuum evaporation of SiO powder is an ideal technique not only to form oxide at low temperature but also to form an abrupt interface with the substrate. The latter feature of evaporation is suitable to form thin gate oxide for Si MOSFETs and gate oxide on compound semiconductors. High-quality SiO₂ on compound semiconductors helps development of MOSFETs made of compound semiconductors, which were longed for to be commercially available. The evaporation is not much used to form SiO₂ for MOSFETs in spite of its many advantages, because quality of SiO₂ formed by evaporation of SiO is too poor to be used as gate oxide. Unlike the commercial SiO powder, the newly developed SiO nanopowder, made by thermal CVD using SiH₄ and O₂, consists of spherical particles with sizes less than 50 nm. It does not contain any Si nanocrystals but small molecular Si networks. Such molecular Si networks are easily thermally or optically decomposed. This makes the deposited oxide more free from Si nanocrystals, which usually degrade the insulating property of the oxide. The SiO₂ thin films formed by evaporation of the SiO nanopowder have demonstrated great potential for application to MOSFETs on plastic substrates and GaN epilayers.     

Effect of Alcohol-Assisted Annealing on the Quality of Silicon Oxide Thin Film

Silicon oxide thin films have been formed by use of the reaction between spin-coated silicone oil and ozone gas at atmospheric pressure and low temperature (250°C). Films formed at this temperature contained Si–OH bonds, owing to inadequate dehydration. To remove the Si–OH bonds at low temperature, the sample was dipped in ethanol at room temperature for 15 min then annealed on a hot plate at 250°C in methanol gas for 30 min. This treatment effectively dissociated the Si–OH bonds. It is believed the Si–OH bonds are replaced by Si-OCH₃ bonds during the alcohol-assisted annealing. The leakage current of the metal-oxide-semiconductor after alcohol-assisted annealing was improved and the hysteresis width was reduced. This indicated that the number of trap sites owing to Si–OH bonds was reduced.     

VLP／CVD低温硅外延

研究了VLP／CVD低温硅外延生长技术,利用自制的VLP／CVD设备,在低温条件下,成功地研制出晶格结构完好的硅同质结外延材料。扩展电阻、X射线衍射谱和电化学分布研究表明,在低温下（T＜800℃）应用VLP／CVD技术,可以生长结构完好的硅外延材料,且材料生长界面的杂质浓度分布更陡峭。     

Light emission from Si/SiO2 superlattices fabricated by RPECVD

Si/SiO₂ superlattices that exhibit intense luminescence properties were fabricated by remote plasma enhanced chemical vapor deposition. (RPECVD) and subsequent rapid thermal annealing for silicon crystallization. The effects of charge carrier confinement like blue shifting of the PL spectra and intensity increase with decreasing Silicon quantum well thickness are observed in low temperature photoluminescence experiments. The Si/SiO₂ interface quality is calculated from capacitance voltage (CV) measurements on metal oxide semiconductor teststructures showing excellent layer and Si/SiO₂ interface properties. The Si crystallization process is investigated and analyzed by Raman and transmission electron microscopy. Decreasing the Si quantum well thickness to 2 nm leads to light emission at room temperature.     

锂离子电池用蛋黄-壳结构硅碳负极材料进展

硅材料具有高理论容量、低工作电压、储量丰富和环境友好等优点,是最有潜力的锂离子电池负极材料之一。然而,硅在锂化/去锂化过程中会产生超过300%的体积膨胀,从而导致硅颗粒粉化和容量快速衰减。近年来,一类新型的蛋黄-壳结构硅碳复合材料引起了广泛的研究关注,这种结构可缓解嵌锂过程中的体积膨胀,提高材料的循环稳定性。本文对蛋黄-壳结构的硅碳负极材料进行了分类和介绍,分析了蛋黄-壳结构硅碳材料的制备方法。阐述了蛋黄-壳结构参数对材料储锂性能的影响。指出通过开发低成本和环境友好的制备工艺、纳-微结构设计和结构参数优化,有望获得性能更优的新型蛋黄-壳结构硅碳负极材料,进一步推动硅碳负极材料的产业应用。     

Specific features of doping with antimony during the ion-beam crystallization of silicon

A method of doping during the growth of thin films by ion-beam crystallization is proposed. By the example of Si and Sb, the possibility of controllably doping semiconductors during the ion-beam crystallization process is shown. A calibrated temperature dependence of the antimony vapor flow rate in the range from 150 to 400°C is obtained. It is established that, an increase in the evaporator temperature above 200°C brings about the accumulation of impurities in the layer growth direction. Silicon layers doped with antimony to a concentration of 10¹⁸ cm^–3 are grown. It is shown that, as the evaporator temperature is increased, the efficiency of the activation of antimony in silicon nonlinearly decreases from ~10⁰ to ~10^–3.