芯片内互连线计算中的一种算法实现

文章解决了将"变方向隐式方法的三维时域有限差分法"(3D ADI-FDTD)应用于高速芯片内互连线的电磁场计算中很多关键问题,包括源的产生方案及其数值结构,具体边界吸收条件的差分格式.特别是针对芯片互连线中的多层介质、多导体线的结构,提出了稀疏的矩阵模型和可变网格的划分.数值实验表明,对原有ADI-FDTD方法所做的这些改进,能够在保证适当精度的情况下提高计算速度.     

梯形截面互连线电阻计算公式

本文提出一个梯形截面互连线单位长度电阻随频率变化的计算公式。首先使用数值方法计算得到频率变化时梯形截面互连线单位长度的电阻值,分析梯形截面对互连线电阻的影响,并给出频率变化时导线中电流密度的分布。根据数值方法的计算结果,使用麦夸特方法得到计算梯形截面导线电阻的简单公式,该公式可以用于片上梯形截面互连线电阻的计算。与数值方法相比,该公式计算效率高且能够保证计算精度。     

高速集成电路芯片内互连线的计算机辅助分析

分析了高速集成电路芯片内互连线的时域特性。首先运用全波方法提取互连线的频变等效电路参数。在此基础上运用数值反拉普拉斯变换 ( NILT)法分析互连电路的时域响应。在分析过程中 ,提出或运用了一些提高精度或效率的技术和方法。分析结果表明 ,该方法很适合高速集成电路芯片内互连线的计算机辅助分析。     

矩形截面互连线电阻计算公式

本文提出两个矩形截面互连线单位长度电阻随频率变化的计算公式。利用数值方法计算得到频率变化时矩形截面互连线单位长度的电阻值,根据数值计算结果,使用麦夸特方法首先得到计算矩形截面单根导线电阻的简单公式,该公式可广泛用于分析片上电源网格IR-drop问题。与其它公式相比,该公式在宽频率、大宽长比范围内均有较高精度。另外,本文还得到类似微带的互连线（互连线加上地线）电阻计算公式,该结构是分析片上或封装系统功率传输问题的典型结构。     

一种用于模拟高速互连线瞬态响应的高效数值方法

本文提出用积分求导法（ＤＱＭ）用于分析高速集成电路系统互连线的瞬态响应。ＤＱＭ是一种直接的数值方法,它将某坐标方向上的微分算子用一离散点的函数值加权逼近,将偏微分方程化为常微分方程求解,可有效地用于高速集成电路互连线系统的瞬态分析,其计算效率高于其它数值方法。     

高速集成电路芯片内互连线的计算机辅助分析

分析了高速集成电路芯片内互连线的时域特性。首先营运全波方法提取互连线的频变等效电路参数。在此基础上运用数值反拉普拉斯变换（ＮＩＬＴ）法分析互连电路的时域响应。在分析过程中,提出或运用了一些提出精度或效率的技术和方法。分析结果表明,该方法很适合高速集成电路芯片内至连线的计算机辅助分析。     

一种65nm CMOS互连线串扰分布式RLC解析模型

基于65nm CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了一种互连线耦合串扰分布式RLC解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下,提出了被干扰线远端的串扰数值表达式.基于65nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在2.50%内,能应用于纳米级SOC的计算机辅助设计.     

一种65nm CMOS互连线串扰分布式RLC解析模型

基于65nm CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了一种互连线耦合串扰分布式RLC解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下,提出了被干扰线远端的串扰数值表达式.基于65nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在2.50%内,能应用于纳米级SOC的计算机辅助设计.     

VLSI随机工艺变化下互连线建模与延迟分析

目前互连线的工艺变化问题已成为影响超大规模集成电路性能的重要因素.考虑了互连线工艺变化的空间相关性,将工艺参数变化建模为具有自相关性的随机过程,采用数值仿真及拟合方法得到寄生参数的近似表达式,最后基于Elmore延迟度量分析了随机工艺变化对互连延迟的影响,提出了工艺变化下互连延迟统计特性的估算方法,并通过仿真实验对方法的有效性进行了验证.     

一种基于目标延迟约束缓冲器插入的互连优化模型

基于分布式RLC传输线,提出在互连延迟满足目标延迟的条件下,利用拉格朗日函数改变插入缓冲器数目与尺寸来减小互连功耗和面积的优化模型. 在65nm CMOS工艺下,对两组不同类型的互连线进行计算比较,验证该模型在改善互连功耗与面积方面的优点. 此模型更适合全局互连线的优化,而且互连线越长,优化效果越明显,能够应用于纳米级SOC的计算机辅助设计和集成电路优化设计.     

Crosstalk noise modeling of multiwall carbon nanotube (MWCNT) interconnects using finite-difference time-domain (FDTD) technique

This paper presents an accurate and efficient model for the transient analysis of multiwall carbon nanotubes (MWCNT) using finite-difference time-domain (FDTD) method. The proposed model can be essentially used to analyze the functional and dynamic crosstalk effects of coupled-two MWCNT interconnect lines. Using the proposed model the voltage and current can be accurately estimated at any point on the interconnect line and furthermore, the model can be extended to coupled-n interconnect lines with a low computational cost. Crosstalk induced propagation delay, peak voltage, and its timing instance are measured using the proposed model and validated by comparing it to the HSPICE simulations. Over a random number of test cases it is observed that the average error in estimating the noise peak voltage on a victim line is less than 1%. The proposed model is extremely useful for accurate estimation of crosstalk induced performance parameters of MWCNT interconnects.     

Analysis of high-speed interconnects using efficient multipointPade approximation

An efficient method is presented for analysis of large interconnect circuits including lossy coupled transmission lines. Based on multipoint Pade approximations and a new expansion point search algorithm, the method can obtain single close-form frequency-domain and transient solutions of the interconnect problem with a minimum of frequency expansion points     

Pulsed wave interconnect

Pulsed wave interconnect is proposed for global interconnect applications. Signals are represented by localized wave-packets that propagate along the interconnect lines at the local speed of light to trigger the receivers. Energy consumption is reduced through charging up only part of the interconnect lines and using the voltage doubling property of the receiver gate capacitances. In a 0.18-/spl mu/m CMOS technology case study, SPICE simulations show that pulsed wave interconnect can save up to 50% of energy and /spl sim/30% of chip area in comparison with the repeater insertion method. A proposed signal splitting structure provides reasonable isolations between different receivers. Measured S-parameters of 3.8-mm interconnect lines fabricated through CMOS foundry showed that the distortion and attenuation of a pico second signal are much less serious than the theoretical predictions. Pulsed wave interconnect also enables time division application of a single line to boost its bit rate capacity. The use of nonlinear transmission lines (NLTL) is also proposed to overcome pulse broadening and attenuation caused by dispersion and frequency-dependent losses. Pulsed waves on an NLTL may be generated, transmitted, split and detected with components realizable in bulk and SOI CMOS technologies. Tapered NLTL can be used for pulse compression. NLTL edge sharpening abilities may be applicable for signal rise time control.     

Analysis of read speed latency in 6T-SRAM cell using multi-layered graphene nanoribbon and cu based nano-interconnects for high performance memory circuit design

In this study, we designed a 6T-SRAM cell using 16-nm CMOS process and analyzed the performance in terms of read-speed latency. The temperature-dependent Cu and multilayered graphene nanoribbon (MLGNR)-based nano-interconnect materials is used throughout the circuit (primarily bit/bit-bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano-interconnects with different interconnect lengths (from 10 μm to 100 μm), for reading-0 and reading-1 operations. To execute the reading operation, the CMOS technology, that is, the16-nm PTM-HPC model, and the16-nm interconnect technology, that is, ITRS-13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high-speed memories using different nano-interconnect materials.     

Optimization of Driver Preemphasis for On-Chip Interconnects

In modern digital systems, on-chip interconnects have become the system bottleneck, limiting the performance of high-speed clock distributions and data communications in terms of speed and power dissipation. An inverse signaling analysis is developed to optimize the driving signal waveforms for lossy interconnects. By specifying the performance parameters, i.e., the signal swing and edge rate of the interconnect output signal, the corresponding input signals can be derived analytically. The result can be used to guide and optimize the design of interconnect preemphasis drivers. Numerical examples are shown for both lossy RC and RLC distributed lines. Analysis shows that optimized driving voltage and current can increase the interconnect bandwidth without voltage overshoot at the output. The significance of an interconnect inductance is also evaluated with this technique.     

A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis

Although three-dimensional (3-D) partial inductance modeling costs have decreased with stable, sparse approximations of the inductance matrix and its inverse, 3-D models are still intractable when applied to full chip timing or crosstalk analysis. The 3-D partial inductance matrix (or its inverse) is too large to be extracted or simulated when power-grid cross-sections are made wide to capture proximity effect and wires are discretized finely to capture skin effect. Fortunately, 3-D inductance models are unnecessary in VLSI interconnect analysis. Because return currents follow interconnect wires, long interconnect wires can be accurately modeled as two-dimensional (2-D) transmission lines and frequency-dependent loop impedances extracted using 2-D methods . Furthermore, this frequency dependence can be approximated with compact circuit models for both uncoupled and coupled lines. Three-dimensional inductance models are only necessary to handle worst case effects such as simultaneous switching in the end regions. This paper begins by explaining and defending the 2-D modeling approach. It then extends the extraction algorithm to efficiently include distant return paths. Finally, a novel synthesis technique is described that approximates the frequency-dependent series impedance of VLSI interconnects with compact circuit models suitable for timing and noise analysis.     

Analytical models and algorithms for the efficient signal integrity verification of inductance-effect-prominent multicoupled VLSI circuit interconnects

Novel signal integrity verification models and algorithms for inductance-effect- prominent RLC interconnect lines are developed by using a traveling-wave-based waveform approximation (TWA) technique. The multicoupled line responses are decoupled into the eigenmodes of the system in order to exploit the TWA technique. Then, the response signals are mathematically represented by the linear combination of each eigenmode response based on TWA, followed by reporting the signal integrity models and algorithms for the multicoupled lines. The signal integrity of VLSI circuit interconnects is complicatedly correlated with input signal switching-patterns, layout geometry, and termination conditions. It is shown that the technique can be efficiently employed for complicated multicoupled interconnect lines with various termination conditions and the signal transients based on the technique have excellent agreement with SPICE simulations. Thus, with the proposed technique, the switching-dependent signal delay, crosstalk, ringing, and glitches of the inductance-effect-prominent RLC interconnect lines can be accurately as well as efficiently determined.     

Analytical thermal model for multilevel VLSI interconnectsincorporating via effect

The authors present compact analytical thermal models for estimating the temperature rise of multilevel VLSI interconnect lines incorporating via effect. The impact of vias has been modeled using (1) a characteristic thermal length and (2) an effective thermal conductivity of ILD (interlayer dielectric), k_ILD,eff, with k _ILD,_eff=k_ILDη/, where η is a physical correction factor, with 0<η<1. Both the spatial temperature profile along the metal lines and their average temperature rise can be easily obtained using these models. The predicted temperature profiles are shown to be in excellent agreement with the three-dimensional (3-D) finite element thermal simulation results. The model is then applied to estimate the temperature rise of densely packed multilevel interconnects. It is shown that for multilevel interconnect arrays, via density along the lines can significantly affect the temperature rise of such interconnect structures