光总线交换网络输出排队两级缓冲结构与性能分析

为了解决核心路由器高速无阻塞光总线交换网络体系结构中的高速大容量分组缓冲这一关键技术难题,本文提出了基于SRAM技术和DRAM技术相结合的输出排队分组两级缓冲结构及相关LBF-MMA存储器管理算法,并利用实测的网络流量数据对该缓冲技术的性能进行了仿真分析.分析表明,两级缓冲结构较好地解决了光总线交换网络中分组缓冲高速度与大容量之间的矛盾,对高速路由器技术的发展也具有一定的指导意义.     

带VOQ的输入队列交换网络中的分组调度算法研究

交换技术已经成为高速路由器的核心技术。本文基于目前高速交换技术所采用的主要体系结构,带有虚拟输出缓冲队列(VOQ)的输入队列交换结构,分析已经存在的各种调度算法的性能,并设计基于遗传算法的调度策略,提供IP数据网络的QoS对吞吐量和抖动的保障。     

缓冲气体对光泵远红外激光器能量交换的影响

基于分子振动弛豫的理论,完善了缓冲气体的作用模型。利用半经典密度矩阵理论与量子力学理论,研究了缓冲气体对光泵远红外激光(FIR)激光过程的作用机理,计算了缓冲气体作用下小型光泵FIR激光器的能量交换过程以及气压等工作参数对输出光强的影响,得出了优化规律,并进行了实验验证。结果表明,适当的缓冲气体可缩短工作气体分子的振动弛豫时间,提高光泵FIR激光器的能量转换效率,使FIR激光信号得到更大的输出。在最佳混合气体比例与最佳工作气体下,可以获得最大的FIR激光信号输出。     

基于FPGA的音频交换混合矩阵设计

提出了一种基于FPGA的音频交换混合矩阵的设计思路,通过运用数字音频信号采样及处理技术实现了16×16的音频信号交换。文章分析了交换技术原理,并基于该原理构建交换混合矩阵的数学模型,并对系统设计实现方案进行了详细的论述。方案中使用了FPGA芯片,以及音量控制、数/模转换及模/数转换芯片。本方案已进行实物验证,其输入输出延迟≤700μs,通频带20 Hz~38.44 kHz。该矩阵现已在多个系统中使用。     

光开关矩阵在自动交换光网络中的应用

自动光交换网络是光网络的发展趋势,其核心技术是光开关矩阵。光开关矩阵是智能光交叉连接设备和可重构光分插复用器核心技术,是构建自动交换光网络的基础。主要介绍了大规模商用的光开关矩阵的技术特点及其在自动交换光网络中的应用。     

磁性材料、超导材料和器件

TM271,TB43 2003040086不同缓冲层对NIFe/FeMn双层膜交换招合场的影响/李明华,于广华,朱逢吾.(2}姜宏伟,(21赖武彦(北京科技大学)11真空科学与技术学报.一2 002,22(l).一65一68采用磁控溅射方法制备了NIFe/FeMn双层膜,分别以Ta,Cu为缓冲层,Ta作为保护层.实验发现,以Ta为缓冲层的NIFe/FeMn双层膜的交换藕合场比以Cu为缓冲层的N iFe/FeMn双层膜的交换藕合场大,而矫顽力却很小.文中分别从织构、界面粗糙度、界面偏聚等几方面对其中的原因进行了分析.除不同缓冲层引起的织构、界面粗糙度不同对交换祸合场有影响外,不同缓冲层引起的…     

带VOQ的输入队列交换网络中的分组调度算法研究

交换技术已经成为高速路由器的核心技术。本文基于目前高速交换技术所采用的主要体系结构，带有虚拟输出缓冲队列（VOQ）的输入队列交换结构，分析已经存在的各种调度算法的性能，并设计基于遗传算法的调度策略，提供IP数据网络的QoS对时延抖动的保障。     

地址相减型宽带交换矩阵

近年来，宽带综合业务数字网（BISDN）的研究非常活跃。宽带交换技术是BISDN中的关键技术之一，而其中的难点是宽带交换矩阵。过去，已有许多宽带交换矩阵的设计，例如Banyan网络等。但这些矩阵都有不足之处。本文提出一种自选路由、无堵塞、高速、大容量矩阵开关的拓扑结构和控制算法，并对硬件电路的实现进行了考虑。这个矩阵能够实现1对1、1对N、N对1、N对N的连接，并且具有控制算法简单、能够检测故障、对称性好、易集成等优点。     

基于SRAM的核心路由器交换矩阵输入端口设计

交换矩阵是核心路由器的重要组成部分,为了避免来自不同输入端口的信元同时发往同一个输出端口,需要在输入端口设置缓冲区,即输入排队交换结构。基于静态随机存储器完成了交换矩阵输入端口虚拟输出队列（VOQ）的设计,该设计可以降低核心路由器交换芯片的面积,提高输入端口缓冲区信元的响应速率,并通过DE-115开发板完成对设计的验证。     

捷普网络信息审计系统优势分析

捷普网络信息审计系统采用Zero-Copy和实时缓冲技术：采用加固和定制的安全操作系统,通过零拷贝技术减少系统调用和CPU的负载,通过实时多级缓冲技术减少与存储系统的交换次数,提高设备的吞吐能力和峰值响应能力。     

Maximum zeros scheduling for satellite switch TDMA

A scheduling technique suitable for preassignment in satellite switched time division multiple access (SS-TDMA) systems is presented. As many uninterrupted bursts as are feasible are transmitted per configuration of the switch matrix. For small switch matrices (up to 6*6) this technique usually requires fewer reconfigurations than previous methods.<>     

一种星地一体的高速星载标签交换机流量控制机制的设计与仿真

为了优化大容量星载交换机的设计,提出了一种星载标签交换技术体制,针对该体制建立了星地一体化卫星网络的队列模型和流量控制机制,根据星载交换机存储资源使用状态调整地面网络设备队列调度权重,降低星载交换机存储资源使用量和丢包率.使用NS2软件仿真分析了长延迟条件下星上缓存队列阈值、星上缓存区容量、地面设备队列调度权重之间的关系.为星载标签交换机和星地一体化网络的设计提供了参考依据.     

High-Speed Time Division Switch for 32-Mbit/s Bearer Rate Signals

This paper describes the high-speed time division switch employed in a 32-Mbit/s bearer signal communications system. System performance is realized by using three technologies. The first is a switch structure referred to as a 2-RAM 2-bank structure which ensures high-speed performance by increasing switching throughput four times over that of the basic structure. The second is the inclusion in the switch of two types of peripheral logic developed using Si-bipolar super-self-aligned process technology. The third is high-speed synchronous transmission of data. A large channel capacity time division switching network is also discussed. In conjunction with the network, these technologies make it possible to realize the ISDN time division switches necessary for such services as TV and high-definition TV communications.     

光交换的时间及空间结构分析

拓扑学上的光网络由边(光传输)和节点(光交换)组成。从业务属性出发,基于连接和无连接方式,分析了光交换的时间结构,包括光分组和光突发的时间结构,以及不同动态性的光电路交换的时长及其度量标准,结合实验结果分析了最短光电路交换的时长极限。从多端口和大容量的要求出发,重点讨论了基于微电子机械系统(MEMS)开关、波长选择开关(WSS)和阵列波导光栅(AWG)的三种光交换结构。分析了光交换结构的扩展方法,并讨论了光交换的几个具有挑战性的问题,包括缓存和能耗问题。通过分析,希望从时间和空间两个维度更清晰地认识光交换的本质及其与电交换的异同。     

一种新颖双馈电型PIN开关

微波光电二极管（PIN）开关速度和功率容量是相互矛盾的2个指标,为同时兼顾改善2个指标,结合半导体器件特性,采取PIN管芯两极同时馈电的设计形式（即双馈电型开关）,经过优化设计,研制出2 GHz～6 GHz单刀双掷PIN开关。与传统型开关电路相比,开关速度和功率容量都得到较好提升,为后续的工程应用奠定了基础。     

Architecture design,performance analysis and VLSI implementation of a reconfigurable shared buffer for high‐speed switch/router

Modern switches and routers require massive storage space to buffer packets. This becomes more significant as link speed increases and switch size grows. From the memory technology perspective, while DRAM is a good choice to meet capacity requirement, the access time causes problems for high‐speed applications. On the other hand, though SRAM is faster, it is more costly and does not have high storage density. The SRAM/DRAM hybrid architecture provides a good solution to meet both capacity and speed requirements. From the switch design and network traffic perspective, to minimize packet loss, the buffering space allocated for each switch port is normally based on the worst‐case scenario, which is usually huge. However, under normal traffic load conditions, the buffer utilization for such configuration is very low. Therefore, we propose a reconfigurable buffer‐sharing scheme that can dynamically adjust the buffering space for each port according to the traffic patterns and buffer saturation status. The target is to achieve high performance and improve buffer utilization, while not posing much constraint on the buffer speed. In this paper, we study the performance of the proposed buffer‐sharing scheme by both a numerical model and extensive simulations under uniform and non‐uniform traffic conditions. We also present the architecture design and VLSI implementation of the proposed reconfigurable shared buffer using the 0.18 µm CMOS technology. Our results manifest that the proposed architecture can always achieve high performance and provide much flexibility for the high‐speed packet switches to adapt to various traffic patterns. Furthermore, it can be easily integrated into the functionality of port controllers of modern switches and routers. Copyright © 2008 John Wiley & Sons, Ltd.     

利用Bit-Slice技术实现ASON大容量交叉

研究了ASON大容量交叉的实现方法.首先说明了ASON大容量交叉的意义,确定了利用电-光-电的交叉实现方案.随后介绍了两种扩充交叉容量的方法:三级CLOS交叉矩阵与Bit-S1ice交叉矩阵.经比较选择Bit-Slice交叉矩阵实现大容量交叉并给出了方案的构成框图及各部分的功能描述.最后提出了实现更大容量交叉的建议与方法.     

Experimental characteristics of optical crosspoint switch matrix and its applications in optical packet switching

This paper presents the experimental results of the switching performances of the fast reconfigurable optical crosspoint switch (OXS) matrix. This paper demonstrates unicast optical packet switching for a 10-Gb/s payload at various modulation formats and a 155-Mb/s nonreturn-to-zero label. Reconfigurable time as fast as 2 ns is achieved because of the optimized control circuit and device fabrication. The power and wavelength dependence for the payload and the capability of multihop operation are investigated as well. The functionalities of the OXS acting as an optical switch and an optical buffer are demonstrated in the optical network node experiment. Very good switching property is obtained for the OXS, which clearly validates OXS as a potential technique for future high-speed Internet-protocol-over-wavelength-division-multiplexing networks.     

Dynamic bandwidth allocation scheme for multiple real‐time VBR videos over ATM networks

This paper considers VBR transmission of multiple real‐time videos over ATM networks. Multiple real‐time VBR video sources are multiplexed into an ATM switch to transmit cells into the network. Given the ATM switch capacity, the problem is to dynamically allocate the required channel bandwidth for each video source such that the encoder buffer occupancy is maintained at a target level. To solve the problem, we present a mathematical formulation and propose an algorithm for the bandwidth allocation. To allocate a suitable bandwidth at a given control period, QoS demand levels and traffic characteristics of the video sources are considered. The performance of the proposed scheme is examined in terms of the number of encoder rate controls required and the gap between the target and the current buffer occupancy at each control period. Numerical results are analyzed for different QoS environments as well as different levels of target buffer, ATM switch capacity, buffer size and leaky bucket token rate. This revised version was published online in June 2006 with corrections to the Cover Date.     

Realization of large capacity ATM switches

Large-capacity ATM switches, with switching capacity in excess of 40 Gb/s or 100 Gb/s, are becoming an essential part of network growth. To realize such switches requires technology know-how as well as implementation trade-off considerations. This article provides a system-level exploration of large-capacity ATM switches in terms of switch fabric scalability, cell buffer management, buffer design trade-off, call processing capabilities, and future trends in switch design