GPS接收机镜像信号抑制

分析了GPS接收机镜像信号抑制的要求,设计应用于低中频GPS接收机的镜像抑制复数滤波器.滤波器基于OTA-C双二次结构,通过线性变换实现频率搬移.采用了带源极负反馈的全差分跨导器以扩大输入线性范围.设计了基于环形振荡器的数字调谐锁相环以减小滤波器频率偏差.电路采用0.18μm CMOS工艺实现.测试结果表明,滤波器带宽为3.1MHz,偏移5MHz抑制为50dB,频率修调误差小于±1.5%.镜像抑制大于35dB.1.8V电源电压下滤波器和修正电路电流分别为0.82mA和0.23mA.     

A 4th-order reconfigurable analog baseband filter for software-defined radio applications

This paper presents a 4th-order reconfigurable analog baseband filter for software-defined radios.The design exploits an active-RC low pass filter（LPF） structure with digital assistant,which is flexible for tunability of filter characteristics,such as cut-off frequency,selectivity,type,noise,gain and power.A novel reconfigurable operational amplifier is proposed to realize the optimization of noise and scalability of power dissipation.The chip was fabricated in an SMIC 0.13μm CMOS process.The main filter and frequency calibration circuit occupy 1.8×0.8 mm² and 0.48×0.25 mm² areas,respectively.The measurement results indicate that the filter provides Butterworth and Chebyshev responses with a wide frequency tuning range from 280 kHz to 15 MHz and a gain range from 0 to 18 dB.An IIP3 of 29 dBm is achieved under a 1.2 V power supply.The input inferred noise density varies from 41 to 133 nV/（Hz）^1/2 according to a given standard,and the power consumptions are 5.46 mW for low band（from 280 kHz to 3 MHz） and 8.74 mW for high band（from 3 to 15 MHz） mode.     

片上自动调谐的可编程有源RC滤波器

研制了一款可编程6阶巴特沃斯有源RC滤波器.为提高滤波器中运算放大器的增益带宽积,设计了一种新型的前馈补偿运算放大器.为消除工艺偏差和环境变化对截止频率的影响,设计了一种片上数字控制频率调谐电路,并采用TSMC 0.18 μm CMOS工艺进行了流片.滤波器采用低通滤波结构,测试结果表明,3 dB截止频率为1～32 MHz,步进1 MHz,带内增益0 dB,带内纹波0.8 dB,2倍带宽处带外抑制不小于24 dBc,5倍带宽处带外抑制不小于68 dBc,滤波器等效输入噪声为340 nV/√Hz@1MHz,调谐误差为±3％.滤波器裸芯片面积0.87 mm×1.05 mm.采用1.8V电源电压,滤波器整体功耗小于20 mW.     

三阶级联复数有源RC带通滤波器

采用0.18μmCMOS工艺设计了一款应用在无线传网中的三阶级联有源RC复数带通滤波器,同时设计了自动频率调谐电路(AFT)。该滤波器采用的是切比雪夫逼近函数予以实现。在5比特数字控制码开关电容阵列的控制下,AFT电路即可完成对主体滤波器电路频率变化的校正。仿真结果显示,滤波器的中心频率稳定在2MHz,通带带宽为2MHz,镜像抑制比大于34dB,相邻信道阻带衰减大于34dB,通带纹波小于1dB,消耗电流为2.3mA,工作电源电压为1.8V。     

Design of Monolithic Tunable CMOS Band-Pass Filter Using Current Feedback Operational Amplifiers

We propose in this paper a tunable second order band-pass filter based on two CMOS current feedback operational amplifiers (CFOAs). The CFOA includes a novel offset compensation technique. A digital building block is implemented in the proposed band-pass filter to tune its central frequency. An important feature of the adopted tuning procedure is the ability to tune the filter without affecting other characteristics such as gain, phase and quality factor. The band-pass filter topology is validated with a configuration where the central frequency is tuned from 60 MHz to 95 MHz with frequency steps of 5 MHz. Measurements of the offset-compensated CFOA are promising, and simulation results of the CFOA-based band-pass filter using the 0.18 μ m CMOS process confirm our theoretical analysis.     

一种低功耗自动频率修正的复数滤波器设计

采用当前主流的0.18μm RFCMOS工艺,设计实现了一款低功耗五阶OTA-C复数滤波器电路,该电路应用于低中频结构的GPS射频前端芯片中。滤波器的频率修正电路没有采用基于锁相环的常规结构,而是设计了一种带有频率修正功能的自偏置电流基准,来补偿工艺、温度变化的影响。滤波器的带宽为3MHz,中心频率为4.092MHz,镜像抑制大于30dB,10MHz频率处的阻带抑制大于40dB。滤波器的通带增益为10dB,消耗的总电流为0.8mA,工作电压为1.8V。理论仿真结果和测试结果能够很好地符合。     

DDS信号发生器中椭圆低通滤波器的设计

本文基于DDS技术的基本原理,对DDS信号发生器中所用的低通滤波器进行了设计.采用了截止特性陡峭的7阶椭圆函数低通滤波器,该滤波器的3 d B截止频率为120MHz,在145MHz处的衰减为60dB,且通带内纹波小于0.2dB.通过Multisim2001仿真研究表明:其幅频特性好,具有快速的衰减性.     

A widely tunable continuous-time LPF for a direct conversion DBS tuner

A continuous-time 7th-order Butterworth Gm-C low pass filter (LPF) with on-chip automatic tuning circuit has been implemented for a direct conversion DBS tuner in 0.35μm SiGe BiCMOS technology. The filter's -3 dB cutoff frequency f0 can be tuned from 4 to 40 MHz. A novel on-chip automatic tuning scheme has been successfully realized to tune and lock the filter's cutoff frequency. Measurement results show that the filter has -0.5 dB passband gain, +/- 5% bandwidth accuracy, 30 nV/Hz1/2 input referred noise, -3 dBVrms passband IIP3, and 27 dBVrms stopband IIP3. The I/Q LPFs with the tuning circuit draw 13 mA (with f0 = 20 MHz) from 5 V supply, and occupy 0.5 mm2.     

一种基于CMOS CCDVCC Ⅱ的可编程多功能滤波器及可编程测量放大器

介绍了一种新型的电调谐差分电压输入第二代电流传输器.并且用其构成一种电压模式多功能滤波器,可以获得:低通、高通、带通、带阻、全通传输函数.且这种滤波器可以通过调节电流传输器偏置电流独立改变传输函数的品质因素和固有频率.这种多功能滤波器仅仅使用两个CCDVCCⅡ、一个电阻和两个电容构成,且不需要任何元件匹配.而且,可以利...     

An ultra high frequency wideband filter

An ultra high frequency wideband filter was developed and fabricated. High-temperature superconductive film, sputtered in a sapphire substrate, was used as a resonator material. Loss in the filter pass band is 0.7 dB, the filter pass band is 165 MHz, its central frequency is 1877 MHz. The filter topology and amplitude-frequency responses are given.     

A novel pseudo differential transconductor for IEEE 802.11 WLANs

A novel pseudo differential transconductor for multi-mode analog baseband channel selection filter is presented. The highly linear transconductor is designed based on the dynamic source degeneration and predistortion cancellation technique. Meanwhile, wide tuning range is achieved with the current division technique. An LC ladder third-order Butterworth low-pass filter implemented with transconductors and capacitors was fabricated by TSMC 0.18-μm CMOS process. The results show that the filter can operate with the cutoff frequency ranging from 4 to 20 MHz. The tuning range is wide enough for the specifications of IEEE 802.11a/b/g/n Wireless LANs under the consideration of low power consumption and linearity requirement. The maximum power consumption is 3.61 mA at the cutoff frequency of 20 MHz.     

低功耗Zigbee收发器镜像抑制滤波器设计

分析镜像抑制和带外衰减的要求,设计了适用于2.4 GHz Zigbee无线收发前端的镜像抑制滤波器.电路采用7阶巴特沃思OTA-C双二次结构.通过线性变换实现复数滤波.采用交叉耦合输入跨导器,扩大了输入线性范围.为减小滤波器频率偏差,设计了一种锁相环频率修调电路.电路利用0.18 μm CMOS工艺实现.测试结果表明,复数滤波器带宽2.54MHz,镜像抑制大于35 dB,偏移3.5 MHz抑制超过50 dB.在1.8 V电源电压下电流为0.86 mA.     

A dual-mode complex filter for GNSS receivers with frequency tuning

A fifth/seventh order dual-mode OTA-C complex filter for global navigation satellite system receivers is implemented in a 0.18 fxm CMOS process. This filter can be configured as the narrow mode of a 4.4 MHz bandwidth center at 4.1 MHz or the wide mode of a 22 MHz bandwidth center at 15.42 MHz. A fully differential OTA with source degeneration is used to provide sufficient linearity. Furthermore, a ring CCO based frequency tuning scheme is proposed to reduce frequency variation. The measured results show that in narrow-band mode the image rejection ratio (IMRR) is 35 dB, the filter dissipates 0.8 mA from the 1.8 V power supply, and the out-of-band rejection is 50 dB at 6 MHz offset. In wide-band mode, IMRR is 28 dB and the filter dissipates 3.2 mA. The frequency tuning error is less than ±2%.     

平坦通带高频纵向耦合谐振滤波器的研制

应用耦合膜理论,重点研究了纵向耦合谐振滤波器耦合换能器与输入/输出换能器间距对纵向耦合谐振滤波器通带波纹的影响,探讨了制作纵向耦合谐振滤波器中金属铝的干法刻蚀工艺。基于理论模拟得出的结论,文中给出了中心频率为900MHz纵向耦合谐振滤波器频率响应的计算模拟结果和实验测试数据。测得1dB带宽25.9MHz,3dB带宽28.7MHz,阻带抑制达到50dB,插入损耗3.85dB,通带波纹小于0.7dB。实验结果与理论分析相吻合。     

A high-efficiency low-voltage class-E PA for IoT applications in sub-1 GHz frequency range

We present and propose a complete and iterative integrated-circuit and electro-magnetic (EM) co-design methodology and procedure for a low-voltage sub-1 GHz class-E PA. The presented class-E PA consists of the on-chip power transistor, the on-chip gate driving circuits, the off-chip tunable LC load network and the off-chip LC ladder low pass filter. The design methodology includes an explicit design equation based circuit components values'' analysis and numerical derivation, output power targeted transistor size and low pass filter design, and power efficiency oriented design optimization. The proposed design procedure includes the power efficiency oriented LC network tuning, the detailed circuit/EM co-simulation plan on integrated circuit level, package level and PCB level to ensure an accurate simulation to measurement match and first pass design success. The proposed PA is targeted to achieve more than 15 dBm output power delivery and 40% power efficiency at 433 MHz frequency band with 1.5 V low voltage supply. The LC load network is designed to be off-chip for the purpose of easy tuning and optimization. The same circuit can be extended to all sub-1 GHz applications with the same tuning and optimization on the load network at different frequencies. The amplifier is implemented in 0.13 μm CMOS technology with a core area occupation of 400 μm by 300 μm. Measurement results showed that it provided power delivery of 16.42 dBm at antenna with efficiency of 40.6%. A harmonics suppression of 44 dBc is achieved, making it suitable for massive deployment of IoT devices.     

A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction

This paper proposes a fast-settling frequency-presetting PLL frequency synthesizer.A mixed-signal VCO and a digital processor are developed to accurately preset the frequency of VCO and greatly reduce the settling time.An auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current.The digital processor can automatically compensate presetting frequency variation with process and temperature,and control the operation of the auxiliary tuning loop.A 1.2 GHz integer-N synthesizer with 1 MHz reference input Was implemented in a 0.18μm process.The measured results demonstrate that the typical settling time of the synthesizer is less than 3μs,and the phase noise is-108 dBc/Hz@1MHz.The reference spur is-52 dBc.     

Design of low-voltage CMOS continuous-time filter with on-chipautomatic tuning

A technique for designing a low-voltage continuous-time active filter is presented in this paper. In this technique, current sources are added to the inverting or noninverting op-amp terminals such that the op-amp input common-mode voltages can be set close to one of the supply rails to allow low-voltage operation. An automatic frequency and Q tuning technique is proposed for tuning the active filter using programmable capacitor arrays (PCAs). The proposed tuning technique does not require any peak detectors, which are difficult to implement at a low supply voltage. Instead, it uses a few analog comparators, a digital comparator, and a few binary counters to adjust the PCAs. To demonstrate the proposed techniques, a 1-V 1-MHz second-order filter fabricated in a conventional 1.2-μm CMOS process is presented. For a 5-kHz input signal, the filter achieves a THD of -60.2 dB for a peak-to-peak output voltage of 600 mV. The frequency tuning range is between 585 kHz and 1.325 MHz. The measured power consumption for the filter alone consumes about 0.52 mW and for the entire system consumes about 1.6 mW for a supply voltage of ±0.5 V     

单片BiCMOS超高频接收机中锁相环的设计

集成电荷泵锁相环的接收芯片工作在ISM频段：290-470MHz,采用AMS0．8μm BiCMOS工艺,npn管的特征频率为12GHz,横向pnp的特征频率为650MHz。锁相环中鉴频鉴相器和电荷泵的设计方案基本消除了死区。压控振荡器采用LC负阻结构,中心振荡频率为433MHz,调谐范围为290-520MHz,频偏为100kHz时的相位噪声约为-98dBC／Hz．分频器采用堆叠式结构以降低功耗,PLL在5V的工作电压下功耗仅为1．4mA。     

An eighth order channel selection filter for low-IF and zero-IF DVB tuner applications

An eighth order active-RC filter for low-IF and zero-IF DVB tuner applications is presented, which is implemented in Butterworth biquad structure. An automatic frequency tuning circuit is introduced to compensate the cut-off frequency variation using a 6-bit switched-capacitor array. Switched-resistor arrays are adopted to cover different cut-off frequencies in low-IF and zero-IF modes. Measurement results show that precise cut-off frequencies at 2.5, 3, 3.5 and 4 MHz in zero-IF mode, 5, 6, 7 and 8 MHz in low-IF mode can be achieved, 60 dB frequency attenuation can be obtained at 20 MHz, and the in-band group delay agrees well with the simulation. Two-tone testing shows the in-band IM3 achieves -52 dB and the out-band IM3 achieves -55 dB with -11 dBm input power.This proposed filter circuit, fabricated in a SMIC 0.18 μm CMOS process, consumes 4 mA current with 1.8 V power supply.     

频率可调内置天线在手机中的应用

为手机天线设计了一种新颖的频率可调电路,这种设计考虑到影响手机天线设计的几个因素,例如电子开关的偏置的局限和非线性失真.设计和测试了一款能够在850MHz/1800MHz和900MHz/1900MHz之间切换的四频手机天线.天线装配在一块与手机PCB物理尺寸相当的一块印制电路上.调节的电路包括低通滤波器、隔直电容和一只Pin Diode开关.最终设计的天线在两个频带内具有较高的辐射效率和较低的非线性失真.