自对准硅化物CMOS／SOI技术研究

在ＣＭＯＳ／ＳＩＭＯＸＳＯＩ电路制作中引入了自对准钴（Ｃｏ）硅化物（ＳＡＬＩＣＩＤＥ）技术，研究了ＳＡＬＩＣＩＤＥ工艺对ＳＯＩＭＯＳＦＥＴ单管特性和ＣＭＯＳ／ＳＯＩ电路速度性能的影响．实验表明，采用ＳＡＬＩＣＩＤＥ技术能有效地减小ＭＯＳＦＥＴ栅、源、漏电极的寄生接触电阻和方块电阻，改善单管的输出特性，降低ＣＭＯＳ／ＳＯＩ环振电路门延迟时间，提高ＣＭＯＳ／ＳＯＩ电路的速度特性．     

自对准硅化物SOI／CMOS技术研究

在ＳＯＩ／ＣＭＯＳ电路制作中引入了自对准钴硅化物（ＳＡＬＩＣＩＤＥ）技术，研究了ＳＡＬＩＣＩＤＥ工艺对ＳＯＩ／ＭＯＳＦＥＴ单管特性和ＳＯＩ／ＣＭＯＳ电路速度性能的影响。实验表明，ＳＡＬＩＣＩＤＥ技术能有效地减小ＭＯＳＦＥＴ栅、源、漏电极的寄生接触电阻和薄层电阻，改善单管的输出特性，降低ＳＯＩ／ＣＭＯＳ环振电路门延迟时间，提高ＳＯＩ／ＣＭＯＳ电路的速度特性。     

采用多孔氧化硅形成超薄SOI结构的研究

本文采用多孔氧化硅全隔离技术获得了硅膜厚度小于１００ｎｍ、硅岛宽度大于１００μｍ的超薄ＳＯＩ（ＴＦＳＯＩ）结构．用透视电子显微镜剖面分析技术（ＸＴＥＭ）、扩展电阻分析（ＳＲＰ）、喇曼光谱、台阶轮廓仪和击穿电压测量等技术对多孔氧化硅超薄ＳＯＩ结构进行了分析，结果表明其顶层硅膜单晶性好，硅膜和埋层氧化层界面平整．实验表明硅岛的台阶形貌及应力状况取决于阳极化反应条件．在硅膜厚约为８０ｎｍ的ＴＦＳＯＩ材料上制备了ｐ沟ＭＯＳＦＥＴ，输出特性良好．     

极薄SOI MOSFET的2维解析模型

极薄ＳＯＩＭＯＳＦＥＴ的２维解析模型＝Ｔｗｏ－ｄｉｍｅｎｓｉｏｎａｌａｎａｌｙｔｉｃｍｏｄｅｌｉｎｇｏｆｖｅｒｙｔｈｉｎＳＯＩＭＯＳＦＥＴ＇ｓ／［刊，英］／Ｊａｓｏｎ，Ｃ．Ｓ…∥ＩＥＥＥＴｒａｎｓ．ＥｌｅｃｔｒｏｎＤｅｖ－１９９０．３７（９）．－１９...     

深亚微米PESD MOSFET特性研究及优化设计

本文对多晶抬高源漏（ＰＥＳＤ）ＭＯＳＦＥＴ的结构作了描述，并对深亚微米ＰＥＳＤＭＯＳ－ＦＥＴ的特性进行了模拟和研究，看到ＰＥＳＤＭＯＳＦＥＴ具有比较好的短沟道特性和亚阈值特性，其输出电流和跨导较大，且对热载流子效应的抑制能力较强，因此具有比较好的性能．给出了ＰＥＳＤＭＯＳＦＥＴ的优化设计方法．当ＭＯＳＦＥＴ尺寸缩小到深亚微米范围时，ＰＥＳＤＭＯＳ－ＦＥＴ将成为一种较为理想的器件结构     

短沟道CMOS／SIMOX器件及电路的辐照特性研究

利用薄膜全耗尽ＣＭＯＳ／ＳＯＩ工艺成功地研制了沟道长度为１．０μｍ的薄膜抗辐照ＳＩＭＯＸＭＯＳＦＥＴ、ＣＭＯＳ／ＳＩＭＯＸ反相器和环振电路，Ｎ和ＰＭＯＳＦＥＴ在辐照剂量分别为３ｘ１０５ｒａｄ（Ｓｉ）和７ｘ１０５ｒａｄ（Ｓｉ）时的阈值电压漂移均小于１Ｖ，１９级ＣＭＯＳ／ＳＩＭＯＸ环振经过５ｘ１０５ｒａｄ（Ｓｉ）剂量的电离辐照后仍能正常工作，其门延迟时间由辐照前的２３７ｐｓ变为３２８ｐｓ。     

SPRITE探测器时空滤波特性分析

用ＳＰＲＩＴＥ探测器的脉冲响应（格林函数）描述了基于时间频率和空间频率变化的ＳＰＲＩＴＥ探测器光学传递函数（ＯＴＦ）、调制传递函数ＭＴＦ和相位传递函数（ＰＴＦ）,并由此分析了该探测器对红外辐射图像在时间域和空间域的联合滤波特性     

深亚微米PESD MOSFET特性研究及优化设计

本文对多晶抬高源漏（ＰＥＳＤ）ＭＯＳＦＥＴ的结构作了描述，并对深亚微米ＰＥＳＤＭＯＳ－ＦＥＴ的特性进行了模拟和研究，看到ＰＥＳＤＭＯＳＦＥＴ具有比较好的短沟道特性和亚阈值特性，其输出电流和跨导较大，且对热载流子效应的抑制能力较强，因此具有比较好的性能．给出了ＰＥＳＤＭＯＳＦＥＴ的优化设计方法．当ＭＯＳＦＥＴ尺寸缩小到深亚微米范围时，ＰＥＳＤＭＯＳ－ＦＥＴ将成为一种较为理想的器件结构     

低损耗的IGBT／MOSFET并联开关在开关电源中的应用

介绍一种由ＭＯＳＦＥＴ和ＩＧＢＴ组成的新颖的低损耗关联开关的构成，工作原理，以及在高频大功率开关电源中的应用，并比较了使用并联组合开关和使用ＭＯＳＦＥＴ（或ＩＧＢＴ）的损耗，给出了在产品的使用效果。     

性能优良的混合双IGBT,MOSFET驱动器SKHI21／22

德国西门康（ＳＥＭＩＫＲＯＮ）公司生产的ＳＫＨＩ２１／２２混合双路ＩＧＢＴＭＯＳＦＥＴ驱动器具有先进的监控电路，可有效防止ＩＧＢＴ损坏，本文着重了介绍了其内部结构功能和部分典型参数。     

A novel flash EEPROM cell based on trench technology forintegration within power integrated circuits

A flash EEPROM suitable for integration within power integrated circuits (PIC's) is presented. The EEPROM cell uses a trench floating gate to give a large gate charge while using no more silicon area than a conventional flash EEPROM cell. The cell shows good immunity against the induced disturbance voltages which are present in a PIC, and the storage lifetime is greater than ten years at a reading voltage of V_D=2.2 V     

The impact of three-dimensional effects on EEPROM cell performance

Device simulation is used to investigate three-dimensional effects in small electrically erasable programmable read-only memory (EEPROM) cells. Threshold voltage, tunnel currents, write speed, and the effects of misregistration are characterized for a structurally parameterized generic FLOTOX EEPROM cell. The results indicate considerable sensitivity to three-dimensional effects. Design insights for small EEPROM cells are discussed     

A single-poly EEPROM cell in SIMOX technology for high-temperatureapplications up to 250°C

A thin-film SIMOX technology has been used for fabrication of a single-polysilicon EEPROM cell suitable for high-temperature applications. The two transistor cell is composed of a select transistor and a floating gate transistor with 10 nm tunnel oxide. The EEPROM process extension requires only a few steps suitable for embedded memory applications with low cost and turn around time. Endurance and data retention characteristics of the SIMOX EEPROM cell are presented for a temperature of 250°C. The problem of temperature induced leakage currents in the select transistor at elevated temperatures is investigated     

A new architecture for the NVRAM-an EEPROM backed-up dynamic RAM

An architecture for a nonvolatile RAM (NVRAM) suitable for high-density applications is described. In the cell, a dynamic RAM cell is merged into an EEPROM cell. A capacitor is constructed between the control gate and the drain diffusion layer of the FLOTOX-type EEPROM memory cell. The equivalent circuit in the dynamic RAM mode consists of two transistors and a capacitor, which eliminates a dummy cell. A dynamic RAM sense amplifier is used in both modes, and it works as a data latch when data are transferred between the dynamic RAM and the EEPROM. The process of the NVRAM is compatible with ordinary EEPROMs     

A dual-mode sensing scheme of capacitor-coupled EEPROM cell

A dual-mode sensing (DMS) scheme for a capacitor-coupled EEPROM cell is described. A memory cell structure and a sensing scheme are proposed and estimated. The memory cell combines an EEPROM cell with a DRAM cell. The DMS scheme utilizes the charge-mode sensing of the EEPROM cell. Using this DMS technique, the sensing speed can be enhanced by 36% at a cell current of 15 μA by virtue of the additional charge-mode sensing. Furthermore, the stress applied to the tunnel oxide of the memory transistor can be relieved by decreasing the programming voltage and shortening the programming time. Therefore, with this memory cell structure and sensing scheme, it is possible to realize high-speed sensing in low-voltage operation and high endurance     

A high-endurance low-temperature polysilicon thin-film transistorEEPROM cell

A planar type polysilicon thin-film transistor (poly-Si TFT) EEPROM cell with electron cyclotron resonance (ECR) N₂O-plasma oxide has been developed with a low temperature (⩽400°C) process. The poly-Si TFT EEPROM cell has an initial threshold voltage shift of 4 V for programming and erasing voltages of 11 V and -11 V, respectively. Furthermore, the poly-Si TFT EEPROM cell maintains the threshold voltage shift of 4 V after 100 000 program/erase cycles. The excellent high endurance of the fabricated poly-Si TFT EEPROM cell is attributed to the ECR N₂O-plasma oxide with good charge-to-breakdown (Qbd) characteristics     

Electrical/thermal properties of nonplanar polyoxides and theconsequent effects for EEPROM cell operation

The electrical/thermal properties of nonplanar polyoxides and the resulting effects for EEPROM operational margins are reported. The polyoxide between floating gate (FG) and control gate (CG) of FLOTOX-type EEPROM cells is nonplanar because it always contains edges, where CG wraps over FG. At such edges a highly stable electrical passivation of Fowler-Nordheim (FN) leakage currents occurs, which can cause a degradation of EEPROM operational margins, due to an electron discharge mechanism from the FG of charged EEPROM cells during the first charging operation after conventional baking. The EEPROM cell study includes the dependence on repeated passivation/depassivation of the polyoxide, on baking temperature and baking time. It is found that the average magnitude of the electron discharge is reduced after each passivation/depassivation cycle, which points to a progressive increase of the number of electrons captured in deep neutral electron traps at the polyoxide edges. Analysis of the temperature dependence leads to an activation energy (thermal detrapping energy of the electrons) of 1.3 eV for the degradation mechanism of EEPROM cell operational margins as well as the nonplanar polyoxide depassivation     

EEPROM单元辐射机理研究

随着EEPROM存储器件在太空和军事领域的广泛应用,国际上对EEPROM抗辐射性能的研究越来越多。为了满足太空及军事领域的需要,文章分别研究了FLOTOX和SONOS两种EEPROM工艺制成的存储单元在辐射条件下所受的影响,比较了FLOTOX和SONOS单元抗辐射性能的优劣,得出由于FLOTOX单元受工艺和结构的限制,抗辐射性能不如SONOS单元。同时在做抗辐射加固设计时,FLOTOX单元还需要考虑到电压耦合比的问题,且不利于等比例缩小。文章的研究不但满足了目前的工作需要,还为以后抗辐射EEPROM制作提供了理论基础。     

高兼容CMOS工艺嵌入EEPROM技术

电可擦除只读存储器是非易失性存储器。文章介绍了高兼容常规CMOS工艺的一种嵌入式电可擦除只读存储器设计与工艺技术,对电可擦除只读存储器单元、高压MOS器件的结构与技术进行了研究。研究结果表明,我们设计的0．8μm电可擦除只读存储器单元Vpp电压在13V～15V之间能够正常工作,擦写时间小于500μs,读出电流大于160μA／μm;在普通CMOS工艺基础上增加了BN＋埋层、隧道窗口工艺,成功应用于含嵌入电可擦除只读存储器的可编程电路的设计与制造。     

SONOS结构EEPROM单元辐射效应分析

随着EEPROM存储器件在太空和军事领域的广泛应用,对EEPROM抗辐射性能的研究越来越多。为了满足应用的需要,文章比较了FLOTOX和SONOS两种EEPROM工艺制成的存储单元在辐射条件下所受的影响,分析了FLOTOX和SONOS单元抗辐射性能的优劣,得出:SONOS结构的EEPROM单元,其抗辐射性能优于FLOTOX结构。并分析了在辐射条件下,SONOS结构受辐射影响的数学模型。文章的研究不但满足了目前的工作需要,还为以后抗辐射EEPROM研究提供了理论基础。